[RISCV] Use TImmLeaf for csr_sysreg

[wangpc-pp]

And use getTargetConstant to create operands.

This PR addresses comments after committing #82322.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Wang Pengcheng (wangpc-pp)

Changes

And use getTargetConstant to create operands.

This PR addresses comments after committing #82322.

---

Full diff: https://github.com/llvm/llvm-project/pull/82463.diff

3 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+4-4)
• (modified) llvm/lib/Target/RISCV/RISCVISelLowering.h (+2-1)
• (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+1-1)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 87f7813c5d5d59..25a27a91a16358 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -11734,14 +11734,14 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
     SDValue LoCounter, HiCounter;
     MVT XLenVT = Subtarget.getXLenVT();
     if (N->getOpcode() == ISD::READCYCLECOUNTER) {
-      LoCounter = DAG.getConstant(
+      LoCounter = DAG.getTargetConstant(
           RISCVSysReg::lookupSysRegByName("CYCLE")->Encoding, DL, XLenVT);
-      HiCounter = DAG.getConstant(
+      HiCounter = DAG.getTargetConstant(
           RISCVSysReg::lookupSysRegByName("CYCLEH")->Encoding, DL, XLenVT);
     } else {
-      LoCounter = DAG.getConstant(
+      LoCounter = DAG.getTargetConstant(
           RISCVSysReg::lookupSysRegByName("TIME")->Encoding, DL, XLenVT);
-      HiCounter = DAG.getConstant(
+      HiCounter = DAG.getTargetConstant(
           RISCVSysReg::lookupSysRegByName("TIMEH")->Encoding, DL, XLenVT);
     }
     SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 83b1c68eea61ac..407206a0b96e10 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -127,7 +127,8 @@ enum NodeType : unsigned {
   FMAX, FMIN,
 
   // A read of the 64-bit counter CSR on a 32-bit target (returns (Lo, Hi)).
-  // It takes a chain operand.
+  // It takes a chain operand and another two target constant operands (the
+  // low and high parts of the counter).
   READ_COUNTER_WIDE,
 
   // brev8, orc.b, zip, and unzip from Zbb and Zbkb. All operands are i32 or
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 0d2ffac4883a34..e753c1f1add0c6 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -365,7 +365,7 @@ def CSRSystemRegister : AsmOperandClass {
   let DiagnosticType = "InvalidCSRSystemRegister";
 }
 
-def csr_sysreg : RISCVOp, ImmLeaf<XLenVT, "return isUInt<12>(Imm);"> {
+def csr_sysreg : RISCVOp, TImmLeaf<XLenVT, "return isUInt<12>(Imm);"> {
   let ParserMatchClass = CSRSystemRegister;
   let PrintMethod = "printCSRSystemRegister";
   let DecoderMethod = "decodeUImmOperand<12>";

[topperc]

LGTM