[RISCV] Move RISCVVType namespace to TargetParser #83222
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@llvm/pr-subscribers-backend-risc-v @llvm/pr-subscribers-llvm-support Author: Wang Pengcheng (wangpc-pp) ChangesClang and some middle-end optimizations may need these helper This can reduce some duplications. Full diff: https://github.com/llvm/llvm-project/pull/83222.diff 7 Files Affected:
diff --git a/llvm/include/llvm/Support/RISCVISAInfo.h b/llvm/include/llvm/Support/RISCVISAInfo.h
index 46df93d7522602..f574d9fdecb97c 100644
--- a/llvm/include/llvm/Support/RISCVISAInfo.h
+++ b/llvm/include/llvm/Support/RISCVISAInfo.h
@@ -12,6 +12,7 @@
#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/Support/Error.h"
+#include "llvm/Support/MathExtras.h"
#include <map>
#include <string>
@@ -116,6 +117,80 @@ class RISCVISAInfo {
void updateMaxELen();
};
+namespace RISCVII {
+enum VLMUL : uint8_t {
+ LMUL_1 = 0,
+ LMUL_2,
+ LMUL_4,
+ LMUL_8,
+ LMUL_RESERVED,
+ LMUL_F8,
+ LMUL_F4,
+ LMUL_F2
+};
+
+enum {
+ TAIL_UNDISTURBED_MASK_UNDISTURBED = 0,
+ TAIL_AGNOSTIC = 1,
+ MASK_AGNOSTIC = 2,
+};
+} // namespace RISCVII
+
+namespace RISCVVType {
+// Is this a SEW value that can be encoded into the VTYPE format.
+inline static bool isValidSEW(unsigned SEW) {
+ return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
+}
+
+// Is this a LMUL value that can be encoded into the VTYPE format.
+inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
+ return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
+}
+
+unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
+ bool MaskAgnostic);
+
+inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
+ unsigned VLMUL = VType & 0x7;
+ return static_cast<RISCVII::VLMUL>(VLMUL);
+}
+
+// Decode VLMUL into 1,2,4,8 and fractional indicator.
+std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
+
+inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
+ assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL");
+ unsigned LmulLog2 = Log2_32(LMUL);
+ return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
+}
+
+inline static unsigned decodeVSEW(unsigned VSEW) {
+ assert(VSEW < 8 && "Unexpected VSEW value");
+ return 1 << (VSEW + 3);
+}
+
+inline static unsigned encodeSEW(unsigned SEW) {
+ assert(isValidSEW(SEW) && "Unexpected SEW value");
+ return Log2_32(SEW) - 3;
+}
+
+inline static unsigned getSEW(unsigned VType) {
+ unsigned VSEW = (VType >> 3) & 0x7;
+ return decodeVSEW(VSEW);
+}
+
+inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
+
+inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
+
+void printVType(unsigned VType, raw_ostream &OS);
+
+unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
+
+std::optional<RISCVII::VLMUL>
+getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW);
+} // namespace RISCVVType
+
} // namespace llvm
#endif
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index d028302b8c4d94..256c19175dac25 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -1378,3 +1378,90 @@ std::string RISCVISAInfo::getTargetFeatureForExtension(StringRef Ext) {
return isExperimentalExtension(Name) ? "experimental-" + Name.str()
: Name.str();
}
+
+// Encode VTYPE into the binary format used by the the VSETVLI instruction which
+// is used by our MC layer representation.
+//
+// Bits | Name | Description
+// -----+------------+------------------------------------------------
+// 7 | vma | Vector mask agnostic
+// 6 | vta | Vector tail agnostic
+// 5:3 | vsew[2:0] | Standard element width (SEW) setting
+// 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting
+unsigned RISCVVType::encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW,
+ bool TailAgnostic, bool MaskAgnostic) {
+ assert(isValidSEW(SEW) && "Invalid SEW");
+ unsigned VLMULBits = static_cast<unsigned>(VLMUL);
+ unsigned VSEWBits = encodeSEW(SEW);
+ unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7);
+ if (TailAgnostic)
+ VTypeI |= 0x40;
+ if (MaskAgnostic)
+ VTypeI |= 0x80;
+
+ return VTypeI;
+}
+
+std::pair<unsigned, bool> RISCVVType::decodeVLMUL(RISCVII::VLMUL VLMUL) {
+ switch (VLMUL) {
+ default:
+ llvm_unreachable("Unexpected LMUL value!");
+ case RISCVII::VLMUL::LMUL_1:
+ case RISCVII::VLMUL::LMUL_2:
+ case RISCVII::VLMUL::LMUL_4:
+ case RISCVII::VLMUL::LMUL_8:
+ return std::make_pair(1 << static_cast<unsigned>(VLMUL), false);
+ case RISCVII::VLMUL::LMUL_F2:
+ case RISCVII::VLMUL::LMUL_F4:
+ case RISCVII::VLMUL::LMUL_F8:
+ return std::make_pair(1 << (8 - static_cast<unsigned>(VLMUL)), true);
+ }
+}
+
+void RISCVVType::printVType(unsigned VType, raw_ostream &OS) {
+ unsigned Sew = getSEW(VType);
+ OS << "e" << Sew;
+
+ unsigned LMul;
+ bool Fractional;
+ std::tie(LMul, Fractional) = decodeVLMUL(getVLMUL(VType));
+
+ if (Fractional)
+ OS << ", mf";
+ else
+ OS << ", m";
+ OS << LMul;
+
+ if (isTailAgnostic(VType))
+ OS << ", ta";
+ else
+ OS << ", tu";
+
+ if (isMaskAgnostic(VType))
+ OS << ", ma";
+ else
+ OS << ", mu";
+}
+
+unsigned RISCVVType::getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) {
+ unsigned LMul;
+ bool Fractional;
+ std::tie(LMul, Fractional) = decodeVLMUL(VLMul);
+
+ // Convert LMul to a fixed point value with 3 fractional bits.
+ LMul = Fractional ? (8 / LMul) : (LMul * 8);
+
+ assert(SEW >= 8 && "Unexpected SEW value");
+ return (SEW * 8) / LMul;
+}
+
+std::optional<RISCVII::VLMUL>
+RISCVVType::getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW) {
+ unsigned Ratio = RISCVVType::getSEWLMULRatio(SEW, VLMUL);
+ unsigned EMULFixedPoint = (EEW * 8) / Ratio;
+ bool Fractional = EMULFixedPoint < 8;
+ unsigned EMUL = Fractional ? 8 / EMULFixedPoint : EMULFixedPoint / 8;
+ if (!isValidLMUL(EMUL, Fractional))
+ return std::nullopt;
+ return RISCVVType::encodeLMUL(EMUL, Fractional);
+}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
index be9c7d190b55ac..61f8e71710377e 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
@@ -134,93 +134,6 @@ parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) {
} // namespace RISCVFeatures
-// Encode VTYPE into the binary format used by the the VSETVLI instruction which
-// is used by our MC layer representation.
-//
-// Bits | Name | Description
-// -----+------------+------------------------------------------------
-// 7 | vma | Vector mask agnostic
-// 6 | vta | Vector tail agnostic
-// 5:3 | vsew[2:0] | Standard element width (SEW) setting
-// 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting
-unsigned RISCVVType::encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW,
- bool TailAgnostic, bool MaskAgnostic) {
- assert(isValidSEW(SEW) && "Invalid SEW");
- unsigned VLMULBits = static_cast<unsigned>(VLMUL);
- unsigned VSEWBits = encodeSEW(SEW);
- unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7);
- if (TailAgnostic)
- VTypeI |= 0x40;
- if (MaskAgnostic)
- VTypeI |= 0x80;
-
- return VTypeI;
-}
-
-std::pair<unsigned, bool> RISCVVType::decodeVLMUL(RISCVII::VLMUL VLMUL) {
- switch (VLMUL) {
- default:
- llvm_unreachable("Unexpected LMUL value!");
- case RISCVII::VLMUL::LMUL_1:
- case RISCVII::VLMUL::LMUL_2:
- case RISCVII::VLMUL::LMUL_4:
- case RISCVII::VLMUL::LMUL_8:
- return std::make_pair(1 << static_cast<unsigned>(VLMUL), false);
- case RISCVII::VLMUL::LMUL_F2:
- case RISCVII::VLMUL::LMUL_F4:
- case RISCVII::VLMUL::LMUL_F8:
- return std::make_pair(1 << (8 - static_cast<unsigned>(VLMUL)), true);
- }
-}
-
-void RISCVVType::printVType(unsigned VType, raw_ostream &OS) {
- unsigned Sew = getSEW(VType);
- OS << "e" << Sew;
-
- unsigned LMul;
- bool Fractional;
- std::tie(LMul, Fractional) = decodeVLMUL(getVLMUL(VType));
-
- if (Fractional)
- OS << ", mf";
- else
- OS << ", m";
- OS << LMul;
-
- if (isTailAgnostic(VType))
- OS << ", ta";
- else
- OS << ", tu";
-
- if (isMaskAgnostic(VType))
- OS << ", ma";
- else
- OS << ", mu";
-}
-
-unsigned RISCVVType::getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) {
- unsigned LMul;
- bool Fractional;
- std::tie(LMul, Fractional) = decodeVLMUL(VLMul);
-
- // Convert LMul to a fixed point value with 3 fractional bits.
- LMul = Fractional ? (8 / LMul) : (LMul * 8);
-
- assert(SEW >= 8 && "Unexpected SEW value");
- return (SEW * 8) / LMul;
-}
-
-std::optional<RISCVII::VLMUL>
-RISCVVType::getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW) {
- unsigned Ratio = RISCVVType::getSEWLMULRatio(SEW, VLMUL);
- unsigned EMULFixedPoint = (EEW * 8) / Ratio;
- bool Fractional = EMULFixedPoint < 8;
- unsigned EMUL = Fractional ? 8 / EMULFixedPoint : EMULFixedPoint / 8;
- if (!isValidLMUL(EMUL, Fractional))
- return std::nullopt;
- return RISCVVType::encodeLMUL(EMUL, Fractional);
-}
-
// Include the auto-generated portion of the compress emitter.
#define GEN_UNCOMPRESS_INSTR
#define GEN_COMPRESS_INSTR
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index d7f7859ce4399b..180195d6fd5074 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -124,23 +124,6 @@ enum {
TargetOverlapConstraintTypeMask = 3ULL << TargetOverlapConstraintTypeShift,
};
-enum VLMUL : uint8_t {
- LMUL_1 = 0,
- LMUL_2,
- LMUL_4,
- LMUL_8,
- LMUL_RESERVED,
- LMUL_F8,
- LMUL_F4,
- LMUL_F2
-};
-
-enum {
- TAIL_UNDISTURBED_MASK_UNDISTURBED = 0,
- TAIL_AGNOSTIC = 1,
- MASK_AGNOSTIC = 2,
-};
-
// Helper functions to read TSFlags.
/// \returns the format of the instruction.
static inline unsigned getFormat(uint64_t TSFlags) {
@@ -484,61 +467,6 @@ parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
} // namespace RISCVFeatures
-namespace RISCVVType {
-// Is this a SEW value that can be encoded into the VTYPE format.
-inline static bool isValidSEW(unsigned SEW) {
- return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
-}
-
-// Is this a LMUL value that can be encoded into the VTYPE format.
-inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
- return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
-}
-
-unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
- bool MaskAgnostic);
-
-inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
- unsigned VLMUL = VType & 0x7;
- return static_cast<RISCVII::VLMUL>(VLMUL);
-}
-
-// Decode VLMUL into 1,2,4,8 and fractional indicator.
-std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
-
-inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
- assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL");
- unsigned LmulLog2 = Log2_32(LMUL);
- return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
-}
-
-inline static unsigned decodeVSEW(unsigned VSEW) {
- assert(VSEW < 8 && "Unexpected VSEW value");
- return 1 << (VSEW + 3);
-}
-
-inline static unsigned encodeSEW(unsigned SEW) {
- assert(isValidSEW(SEW) && "Unexpected SEW value");
- return Log2_32(SEW) - 3;
-}
-
-inline static unsigned getSEW(unsigned VType) {
- unsigned VSEW = (VType >> 3) & 0x7;
- return decodeVSEW(VSEW);
-}
-
-inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
-
-inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
-
-void printVType(unsigned VType, raw_ostream &OS);
-
-unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
-
-std::optional<RISCVII::VLMUL>
-getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW);
-} // namespace RISCVVType
-
namespace RISCVRVC {
bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index df4c7f7de8a3d2..6b2a00da826d95 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -906,3 +906,22 @@ For example, clang -march=rv32i_v1p0)";
return Captured.find(Expected) != std::string::npos;
}(CapturedOutput, ExpectedOutput));
}
+
+TEST(RISCVVType, CheckSameRatioLMUL) {
+ // Smaller LMUL.
+ EXPECT_EQ(RISCVII::LMUL_1,
+ RISCVVType::getSameRatioLMUL(16, RISCVII::LMUL_2, 8));
+ EXPECT_EQ(RISCVII::LMUL_F2,
+ RISCVVType::getSameRatioLMUL(16, RISCVII::LMUL_1, 8));
+ // Smaller fractional LMUL.
+ EXPECT_EQ(RISCVII::LMUL_F8,
+ RISCVVType::getSameRatioLMUL(16, RISCVII::LMUL_F4, 8));
+ // Bigger LMUL.
+ EXPECT_EQ(RISCVII::LMUL_2,
+ RISCVVType::getSameRatioLMUL(8, RISCVII::LMUL_1, 16));
+ EXPECT_EQ(RISCVII::LMUL_1,
+ RISCVVType::getSameRatioLMUL(8, RISCVII::LMUL_F2, 16));
+ // Bigger fractional LMUL.
+ EXPECT_EQ(RISCVII::LMUL_F2,
+ RISCVVType::getSameRatioLMUL(8, RISCVII::LMUL_F4, 16));
+}
diff --git a/llvm/unittests/Target/RISCV/CMakeLists.txt b/llvm/unittests/Target/RISCV/CMakeLists.txt
index d80d29b7f0dada..b58d605355bad8 100644
--- a/llvm/unittests/Target/RISCV/CMakeLists.txt
+++ b/llvm/unittests/Target/RISCV/CMakeLists.txt
@@ -16,7 +16,6 @@ set(LLVM_LINK_COMPONENTS
add_llvm_target_unittest(RISCVTests
MCInstrAnalysisTest.cpp
- RISCVBaseInfoTest.cpp
RISCVInstrInfoTest.cpp
)
diff --git a/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp b/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
deleted file mode 100644
index 0e4c90caaaefd7..00000000000000
--- a/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
+++ /dev/null
@@ -1,34 +0,0 @@
-//===- RISCVBaseInfoTest.cpp - RISCVBaseInfo unit tests ----------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#include "MCTargetDesc/RISCVBaseInfo.h"
-
-#include "gtest/gtest.h"
-
-using namespace llvm;
-
-namespace {
-TEST(RISCVBaseInfo, CheckSameRatioLMUL) {
- // Smaller LMUL.
- EXPECT_EQ(RISCVII::LMUL_1,
- RISCVVType::getSameRatioLMUL(16, RISCVII::LMUL_2, 8));
- EXPECT_EQ(RISCVII::LMUL_F2,
- RISCVVType::getSameRatioLMUL(16, RISCVII::LMUL_1, 8));
- // Smaller fractional LMUL.
- EXPECT_EQ(RISCVII::LMUL_F8,
- RISCVVType::getSameRatioLMUL(16, RISCVII::LMUL_F4, 8));
- // Bigger LMUL.
- EXPECT_EQ(RISCVII::LMUL_2,
- RISCVVType::getSameRatioLMUL(8, RISCVII::LMUL_1, 16));
- EXPECT_EQ(RISCVII::LMUL_1,
- RISCVVType::getSameRatioLMUL(8, RISCVII::LMUL_F2, 16));
- // Bigger fractional LMUL.
- EXPECT_EQ(RISCVII::LMUL_F2,
- RISCVVType::getSameRatioLMUL(8, RISCVII::LMUL_F4, 16));
-}
-} // namespace
|
|
Is it possible to move them to TargetParser instead? |
Yes, I think we can. But is there any specific reason? |
The Support library shouldn't contain target specific code if possible. The only reason RISCVISAInfo is in there is because TableGen uses it. |
Clang and some middle-end optimizations may need these helper functions. This can reduce some duplications.
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Ping. |
topperc
reviewed
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|
There are some failures: https://lab.llvm.org/buildbot/#/builders/57/builds/33206 |
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Clang and some middle-end optimizations may need these helper
functions.
This can reduce some duplications.