[RISCV] Teach RISCVMakeCompressible handle byte/half load/store for Zcb. #83375
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@llvm/pr-subscribers-backend-risc-v Author: Yeting Kuo (yetingk) ChangesFor targets with Zcb, this patch makes llvm generate more compress c.lb/lbu/lh/lhu/sb/sh instructions. Full diff: https://github.com/llvm/llvm-project/pull/83375.diff 2 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
index af864ba0fbc46f..8a1588980a922b 100644
--- a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
@@ -99,6 +99,14 @@ static unsigned log2LdstWidth(unsigned Opcode) {
switch (Opcode) {
default:
llvm_unreachable("Unexpected opcode");
+ case RISCV::LB:
+ case RISCV::LBU:
+ case RISCV::SB:
+ return 0;
+ case RISCV::LH:
+ case RISCV::LHU:
+ case RISCV::SH:
+ return 1;
case RISCV::LW:
case RISCV::SW:
case RISCV::FLW:
@@ -121,8 +129,14 @@ static uint8_t compressedLDSTOffsetMask(unsigned Opcode) {
// Return true if Offset fits within a compressed stack-pointer based
// load/store.
static bool compressibleSPOffset(int64_t Offset, unsigned Opcode) {
- return log2LdstWidth(Opcode) == 2 ? isShiftedUInt<6, 2>(Offset)
- : isShiftedUInt<6, 3>(Offset);
+ // Compressed sp-based loads and stores only work for 32/64 bits.
+ switch (log2LdstWidth(Opcode)) {
+ case 2:
+ return isShiftedUInt<6, 2>(Offset);
+ case 3:
+ return isShiftedUInt<6, 3>(Offset);
+ }
+ return false;
}
// Given an offset for a load/store, return the adjustment required to the base
@@ -147,6 +161,11 @@ static bool isCompressibleLoad(const MachineInstr &MI) {
switch (MI.getOpcode()) {
default:
return false;
+ case RISCV::LB:
+ case RISCV::LBU:
+ case RISCV::LH:
+ case RISCV::LHU:
+ return STI.hasStdExtZcb();
case RISCV::LW:
case RISCV::LD:
return STI.hasStdExtCOrZca();
@@ -164,6 +183,9 @@ static bool isCompressibleStore(const MachineInstr &MI) {
switch (MI.getOpcode()) {
default:
return false;
+ case RISCV::SB:
+ case RISCV::SH:
+ return STI.hasStdExtZcb();
case RISCV::SW:
case RISCV::SD:
return STI.hasStdExtCOrZca();
diff --git a/llvm/test/CodeGen/RISCV/make-compressible-zbc.mir b/llvm/test/CodeGen/RISCV/make-compressible-zbc.mir
new file mode 100644
index 00000000000000..8121bec3b75e5c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/make-compressible-zbc.mir
@@ -0,0 +1,352 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -o - %s -mtriple=riscv32 -mattr=+zcb -simplify-mir \
+# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=CHECK %s
+# RUN: llc -o - %s -mtriple=riscv64 -mattr=+zcb -simplify-mir \
+# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=CHECK %s
+
+--- |
+ define void @store_common_value_i8(ptr %a, ptr %b, ptr %c) #0 {
+ entry:
+ store i8 0, ptr %a, align 1
+ store i8 0, ptr %b, align 1
+ store i8 0, ptr %c, align 1
+ ret void
+ }
+
+ define void @store_common_value_i16(ptr %a, ptr %b, ptr %c) #0 {
+ entry:
+ store i16 0, ptr %a, align 2
+ store i16 0, ptr %b, align 2
+ store i16 0, ptr %c, align 2
+ ret void
+ }
+
+ define void @store_common_ptr_i8(ptr %p) #0 {
+ entry:
+ store volatile i8 1, ptr %p, align 1
+ store volatile i8 3, ptr %p, align 1
+ store volatile i8 5, ptr %p, align 1
+ ret void
+ }
+
+ define void @store_common_ptr_i16(ptr %p) #0 {
+ entry:
+ store volatile i16 1, ptr %p, align 2
+ store volatile i16 3, ptr %p, align 2
+ store volatile i16 5, ptr %p, align 2
+ ret void
+ }
+
+ define void @load_common_ptr_i8(ptr %p) #0 {
+ entry:
+ %0 = load volatile i8, ptr %p, align 1
+ %a = sext i8 %0 to i32
+ %1 = load volatile i8, ptr %p, align 1
+ %2 = load volatile i8, ptr %p, align 1
+ ret void
+ }
+
+ define void @load_common_ptr_i16(ptr %p) #0 {
+ entry:
+ %0 = load volatile i16, ptr %p, align 2
+ %1 = load volatile i16, ptr %p, align 2
+ %2 = load volatile i16, ptr %p, align 2
+ ret void
+ }
+
+ define void @store_large_offset_i8(ptr %p) #0 {
+ entry:
+ %0 = getelementptr inbounds i8, ptr %p, i8 100
+ store volatile i8 1, ptr %0, align 1
+ %1 = getelementptr inbounds i8, ptr %p, i8 101
+ store volatile i8 3, ptr %1, align 1
+ %2 = getelementptr inbounds i8, ptr %p, i8 102
+ store volatile i8 5, ptr %2, align 1
+ %3 = getelementptr inbounds i8, ptr %p, i8 103
+ store volatile i8 7, ptr %3, align 1
+ ret void
+ }
+
+ define void @store_large_offset_i16(ptr %p) #0 {
+ entry:
+ %0 = getelementptr inbounds i16, ptr %p, i16 100
+ store volatile i16 1, ptr %0, align 2
+ %1 = getelementptr inbounds i16, ptr %p, i16 101
+ store volatile i16 3, ptr %1, align 2
+ %2 = getelementptr inbounds i16, ptr %p, i16 102
+ store volatile i16 5, ptr %2, align 2
+ %3 = getelementptr inbounds i16, ptr %p, i16 103
+ store volatile i16 7, ptr %3, align 2
+ ret void
+ }
+
+ define void @load_large_offset_i8(ptr %p) #0 {
+ entry:
+ %0 = getelementptr inbounds i8, ptr %p, i8 100
+ %a = load volatile i8, ptr %0, align 4
+ %1 = getelementptr inbounds i8, ptr %p, i8 101
+ %b = load volatile i8, ptr %1, align 4
+ %2 = getelementptr inbounds i8, ptr %p, i8 102
+ %c = load volatile i8, ptr %2, align 4
+ %3 = getelementptr inbounds i8, ptr %p, i8 103
+ %d = load volatile i8, ptr %3, align 4
+ ret void
+ }
+
+ define void @load_large_offset_i16(ptr %p) #0 {
+ entry:
+ %0 = getelementptr inbounds i16, ptr %p, i16 100
+ %a = load volatile i16, ptr %0, align 4
+ %1 = getelementptr inbounds i16, ptr %p, i16 101
+ %b = load volatile i16, ptr %1, align 4
+ %2 = getelementptr inbounds i16, ptr %p, i16 102
+ %c = load volatile i16, ptr %2, align 4
+ %3 = getelementptr inbounds i16, ptr %p, i16 103
+ %d = load volatile i16, ptr %3, align 4
+ ret void
+ }
+
+ attributes #0 = { minsize }
+
+...
+---
+name: store_common_value_i8
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11, $x12
+
+ ; CHECK-LABEL: name: store_common_value_i8
+ ; CHECK: liveins: $x10, $x11, $x12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $x13 = ADDI $x0, 0
+ ; CHECK-NEXT: SB $x13, killed renamable $x10, 0 :: (store (s8) into %ir.a)
+ ; CHECK-NEXT: SB $x13, killed renamable $x11, 0 :: (store (s8) into %ir.b)
+ ; CHECK-NEXT: SB $x13, killed renamable $x12, 0 :: (store (s8) into %ir.c)
+ ; CHECK-NEXT: PseudoRET
+ SB $x0, killed renamable $x10, 0 :: (store (s8) into %ir.a)
+ SB $x0, killed renamable $x11, 0 :: (store (s8) into %ir.b)
+ SB $x0, killed renamable $x12, 0 :: (store (s8) into %ir.c)
+ PseudoRET
+
+...
+---
+name: store_common_value_i16
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11, $x12
+
+ ; CHECK-LABEL: name: store_common_value_i16
+ ; CHECK: liveins: $x10, $x11, $x12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $x13 = ADDI $x0, 0
+ ; CHECK-NEXT: SH $x13, killed renamable $x10, 0 :: (store (s16) into %ir.a)
+ ; CHECK-NEXT: SH $x13, killed renamable $x11, 0 :: (store (s16) into %ir.b)
+ ; CHECK-NEXT: SH $x13, killed renamable $x12, 0 :: (store (s16) into %ir.c)
+ ; CHECK-NEXT: PseudoRET
+ SH $x0, killed renamable $x10, 0 :: (store (s16) into %ir.a)
+ SH $x0, killed renamable $x11, 0 :: (store (s16) into %ir.b)
+ SH $x0, killed renamable $x12, 0 :: (store (s16) into %ir.c)
+ PseudoRET
+
+...
+---
+name: store_common_ptr_i8
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: store_common_ptr_i8
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 1
+ ; CHECK-NEXT: SB killed renamable $x11, renamable $x10, 0 :: (volatile store (s8) into %ir.p)
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 3
+ ; CHECK-NEXT: SB killed renamable $x11, renamable $x10, 0 :: (volatile store (s8) into %ir.p)
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 5
+ ; CHECK-NEXT: SB killed renamable $x11, killed renamable $x10, 0 :: (volatile store (s8) into %ir.p)
+ ; CHECK-NEXT: PseudoRET
+ renamable $x11 = ADDI $x0, 1
+ SB killed renamable $x11, renamable $x10, 0 :: (volatile store (s8) into %ir.p)
+ renamable $x11 = ADDI $x0, 3
+ SB killed renamable $x11, renamable $x10, 0 :: (volatile store (s8) into %ir.p)
+ renamable $x11 = ADDI $x0, 5
+ SB killed renamable $x11, killed renamable $x10, 0 :: (volatile store (s8) into %ir.p)
+ PseudoRET
+
+...
+---
+name: store_common_ptr_i16
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: store_common_ptr_i16
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 1
+ ; CHECK-NEXT: SH killed renamable $x11, renamable $x10, 0 :: (volatile store (s16) into %ir.p)
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 3
+ ; CHECK-NEXT: SH killed renamable $x11, renamable $x10, 0 :: (volatile store (s16) into %ir.p)
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 5
+ ; CHECK-NEXT: SH killed renamable $x11, killed renamable $x10, 0 :: (volatile store (s16) into %ir.p)
+ ; CHECK-NEXT: PseudoRET
+ renamable $x11 = ADDI $x0, 1
+ SH killed renamable $x11, renamable $x10, 0 :: (volatile store (s16) into %ir.p)
+ renamable $x11 = ADDI $x0, 3
+ SH killed renamable $x11, renamable $x10, 0 :: (volatile store (s16) into %ir.p)
+ renamable $x11 = ADDI $x0, 5
+ SH killed renamable $x11, killed renamable $x10, 0 :: (volatile store (s16) into %ir.p)
+ PseudoRET
+
+...
+---
+name: load_common_ptr_i8
+body: |
+ bb.0.entry:
+ liveins: $x16
+
+ ; CHECK-LABEL: name: load_common_ptr_i8
+ ; CHECK: liveins: $x16
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $x11 = ADDI $x16, 0
+ ; CHECK-NEXT: dead $x10 = LB $x11, 0 :: (volatile load (s8) from %ir.p)
+ ; CHECK-NEXT: dead $x10 = LB $x11, 0 :: (volatile load (s8) from %ir.p)
+ ; CHECK-NEXT: dead $x10 = LBU killed $x11, 0 :: (volatile load (s8) from %ir.p)
+ ; CHECK-NEXT: PseudoRET
+ dead $x10 = LB renamable $x16, 0 :: (volatile load (s8) from %ir.p)
+ dead $x10 = LB renamable $x16, 0 :: (volatile load (s8) from %ir.p)
+ dead $x10 = LBU killed renamable $x16, 0 :: (volatile load (s8) from %ir.p)
+ PseudoRET
+
+...
+---
+name: load_common_ptr_i16
+body: |
+ bb.0.entry:
+ liveins: $x16
+
+ ; CHECK-LABEL: name: load_common_ptr_i16
+ ; CHECK: liveins: $x16
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $x11 = ADDI $x16, 0
+ ; CHECK-NEXT: dead $x10 = LH $x11, 0 :: (volatile load (s16) from %ir.p)
+ ; CHECK-NEXT: dead $x10 = LH $x11, 0 :: (volatile load (s16) from %ir.p)
+ ; CHECK-NEXT: dead $x10 = LHU killed $x11, 0 :: (volatile load (s16) from %ir.p)
+ ; CHECK-NEXT: PseudoRET
+ dead $x10 = LH renamable $x16, 0 :: (volatile load (s16) from %ir.p)
+ dead $x10 = LH renamable $x16, 0 :: (volatile load (s16) from %ir.p)
+ dead $x10 = LHU killed renamable $x16, 0 :: (volatile load (s16) from %ir.p)
+ PseudoRET
+
+...
+---
+name: store_large_offset_i8
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: store_large_offset_i8
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 1
+ ; CHECK-NEXT: $x12 = ADDI $x10, 96
+ ; CHECK-NEXT: SB killed renamable $x11, $x12, 4 :: (volatile store (s8) into %ir.0)
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 3
+ ; CHECK-NEXT: SB killed renamable $x11, $x12, 5 :: (volatile store (s8) into %ir.1)
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 5
+ ; CHECK-NEXT: SB killed renamable $x11, $x12, 6 :: (volatile store (s8) into %ir.2)
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 7
+ ; CHECK-NEXT: SB killed renamable $x11, killed $x12, 7 :: (volatile store (s8) into %ir.3)
+ ; CHECK-NEXT: PseudoRET
+ renamable $x11 = ADDI $x0, 1
+ SB killed renamable $x11, renamable $x10, 100 :: (volatile store (s8) into %ir.0)
+ renamable $x11 = ADDI $x0, 3
+ SB killed renamable $x11, renamable $x10, 101 :: (volatile store (s8) into %ir.1)
+ renamable $x11 = ADDI $x0, 5
+ SB killed renamable $x11, renamable $x10, 102 :: (volatile store (s8) into %ir.2)
+ renamable $x11 = ADDI $x0, 7
+ SB killed renamable $x11, killed renamable $x10, 103 :: (volatile store (s8) into %ir.3)
+ PseudoRET
+
+...
+---
+name: store_large_offset_i16
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10
+ ; CHECK-LABEL: name: store_large_offset_i16
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 1
+ ; CHECK-NEXT: $x12 = ADDI $x10, 192
+ ; CHECK-NEXT: SH killed renamable $x11, $x12, 8 :: (volatile store (s16) into %ir.0)
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 3
+ ; CHECK-NEXT: SH killed renamable $x11, $x12, 10 :: (volatile store (s16) into %ir.1)
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 5
+ ; CHECK-NEXT: SH killed renamable $x11, $x12, 12 :: (volatile store (s16) into %ir.2)
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 7
+ ; CHECK-NEXT: SH killed renamable $x11, killed $x12, 14 :: (volatile store (s16) into %ir.3)
+ ; CHECK-NEXT: PseudoRET
+ renamable $x11 = ADDI $x0, 1
+ SH killed renamable $x11, renamable $x10, 200 :: (volatile store (s16) into %ir.0)
+ renamable $x11 = ADDI $x0, 3
+ SH killed renamable $x11, renamable $x10, 202 :: (volatile store (s16) into %ir.1)
+ renamable $x11 = ADDI $x0, 5
+ SH killed renamable $x11, renamable $x10, 204 :: (volatile store (s16) into %ir.2)
+ renamable $x11 = ADDI $x0, 7
+ SH killed renamable $x11, killed renamable $x10, 206 :: (volatile store (s16) into %ir.3)
+ PseudoRET
+
+...
+---
+name: load_large_offset_i8
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x16
+
+ ; CHECK-LABEL: name: load_large_offset_i8
+ ; CHECK: liveins: $x16
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $x11 = ADDI $x16, 384
+ ; CHECK-NEXT: dead $x10 = LB $x11, 16 :: (volatile load (s8) from %ir.0)
+ ; CHECK-NEXT: dead $x10 = LB $x11, 20 :: (volatile load (s8) from %ir.1)
+ ; CHECK-NEXT: dead $x10 = LBU $x11, 24 :: (volatile load (s8) from %ir.2)
+ ; CHECK-NEXT: dead $x10 = LBU killed $x11, 28 :: (volatile load (s8) from %ir.3)
+ ; CHECK-NEXT: PseudoRET
+ dead $x10 = LB renamable $x16, 400 :: (volatile load (s8) from %ir.0)
+ dead $x10 = LB renamable $x16, 404 :: (volatile load (s8) from %ir.1)
+ dead $x10 = LBU renamable $x16, 408 :: (volatile load (s8) from %ir.2)
+ dead $x10 = LBU killed renamable $x16, 412 :: (volatile load (s8) from %ir.3)
+ PseudoRET
+
+...
+---
+name: load_large_offset_i16
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x16
+
+ ; CHECK-LABEL: name: load_large_offset_i16
+ ; CHECK: liveins: $x16
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $x11 = ADDI $x16, 384
+ ; CHECK-NEXT: dead $x10 = LB $x11, 16 :: (volatile load (s16) from %ir.0)
+ ; CHECK-NEXT: dead $x10 = LB $x11, 20 :: (volatile load (s16) from %ir.1)
+ ; CHECK-NEXT: dead $x10 = LBU $x11, 24 :: (volatile load (s16) from %ir.2)
+ ; CHECK-NEXT: dead $x10 = LBU killed $x11, 28 :: (volatile load (s16) from %ir.3)
+ ; CHECK-NEXT: PseudoRET
+ dead $x10 = LB renamable $x16, 400 :: (volatile load (s16) from %ir.0)
+ dead $x10 = LB renamable $x16, 404 :: (volatile load (s16) from %ir.1)
+ dead $x10 = LBU renamable $x16, 408 :: (volatile load (s16) from %ir.2)
+ dead $x10 = LBU killed renamable $x16, 412 :: (volatile load (s16) from %ir.3)
+ PseudoRET
+
+...
|
topperc
reviewed
Feb 29, 2024
| @@ -99,6 +99,14 @@ static unsigned log2LdstWidth(unsigned Opcode) { | |||
| switch (Opcode) { | |||
| default: | |||
| llvm_unreachable("Unexpected opcode"); | |||
| case RISCV::LB: | |||
topperc
reviewed
Feb 29, 2024
| ; CHECK-NEXT: $x11 = ADDI $x16, 384 | ||
| ; CHECK-NEXT: dead $x10 = LB $x11, 16 :: (volatile load (s8) from %ir.0) | ||
| ; CHECK-NEXT: dead $x10 = LB $x11, 20 :: (volatile load (s8) from %ir.1) | ||
| ; CHECK-NEXT: dead $x10 = LBU $x11, 24 :: (volatile load (s8) from %ir.2) |
There was a problem hiding this comment.
I think C.LBU can only encode an offset of 0, 1, 2, 3. So this didn't improve compression
…uctions for Zbc. For targets with Zcb, this patch makes llvm generate more compress c.lbu/lh/lhu/sb/sh instructions.
topperc
reviewed
Mar 26, 2024
| ; CHECK-NEXT: SB killed renamable $x11, killed renamable $x10, 0 :: (volatile store (s8) into %ir.p) | ||
| ; CHECK-NEXT: PseudoRET | ||
| renamable $x11 = ADDI $x0, 1 | ||
| SB killed renamable $x11, renamable $x10, 0 :: (volatile store (s8) into %ir.p) |
There was a problem hiding this comment.
store_common_ptr from make-compressible.mir uses an uncompressible register $x16 as the pointer. The pass inserts a copy to $x11 to make the stores compressible.
| ; CHECK-LABEL: name: store_common_ptr_i16 | ||
| ; CHECK: liveins: $x10 | ||
| ; CHECK-NEXT: {{ $}} | ||
| ; CHECK-NEXT: renamable $x11 = ADDI $x0, 1 |
There was a problem hiding this comment.
Same comment as store_common_ptr_i8
| ; CHECK-NEXT: dead $x10 = LB renamable $x16, 0 :: (volatile load (s8) from %ir.p) | ||
| ; CHECK-NEXT: dead $x10 = LBU killed renamable $x16, 0 :: (volatile load (s8) from %ir.p) | ||
| ; CHECK-NEXT: PseudoRET | ||
| dead $x10 = LB renamable $x16, 0 :: (volatile load (s8) from %ir.p) |
There was a problem hiding this comment.
I think we need to use all LBU here to make this test change anything
|
Sorry I had written review comments weeks ago but forgot to finish submitting them. |
topperc
changed the title
topperc
reviewed
Mar 26, 2024
| ; CHECK-LABEL: name: store_common_ptr_i8 | ||
| ; CHECK: liveins: $x10 | ||
| ; CHECK-NEXT: {{ $}} | ||
| ; CHECK-NEXT: renamable $x16 = ADDI $x0, 1 |
There was a problem hiding this comment.
Nothing changed
You need to use x10 for the store value and x16 for the pointer like the existing test from make-compressible.mir
renamable $x10 = ADDI $x0, 1
SW killed renamable $x10, renamable $x16, 0 :: (volatile store (s32) into %ir.p)
renamable $x10 = ADDI $x0, 3
SW killed renamable $x10, renamable $x16, 0 :: (volatile store (s32) into %ir.p)
renamable $x10 = ADDI $x0, 5
SW killed renamable $x10, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p)
PseudoRET
| ; CHECK-LABEL: name: store_common_ptr_i16 | ||
| ; CHECK: liveins: $x10 | ||
| ; CHECK-NEXT: {{ $}} | ||
| ; CHECK-NEXT: renamable $x16 = ADDI $x0, 1 |
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For targets with Zcb, this patch makes llvm generate more compress c.lb/lbu/lh/lhu/sb/sh instructions.