[RISCV] Support scheduling VCIX instructions #83427
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If we don't do anything, the latencies of VCIX instructions will be all 1. Here I just set the latency to a very large number, so the scheduler will treat them costly. Though I still don't know why scheduler doesn't take register presure into consideration.
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I think the cycle simulation in the scheduler is keeping the loads in the pending queue instead of the available queue so they aren't in consideration for scheduling. So they aren't available as choices to reduce register pressure. At the very least all of the VCIX instructions need to go through VCQ and occupy the arithmetic sequencer for VLEN*LMUL/DLEN cycles. |
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Should we add a test case? |
Yeah you are right. And it depends on the implementation of co-processor, so it's really hard to model it staticly in schedule model.
The test should be reduced, it's too large. I just provided a thought/way to fix (temporarily?) the problem, please feel free to create thorough fix as I don't really know the details about x280's microarchitecture. |
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Prefer to #86093. |
If we don't do anything, the latencies of VCIX instructions will be
all 1.
Here I just set the latency to a very large number, so the scheduler
will treat them costly.
Though I still don't know why scheduler doesn't take register pressure
into consideration.
Fixes #83391