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[RISCV] Don't remove extends for i1 indices in mgather/mscatter #83951
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@llvm/pr-subscribers-backend-risc-v Author: Luke Lau (lukel97) Changesi1 is a legal type, but isn't valid for indexed loads and stores. Full diff: https://github.com/llvm/llvm-project/pull/83951.diff 3 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 7da074e055a774..420ddceae5906e 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -20043,8 +20043,9 @@ bool RISCVTargetLowering::shouldRemoveExtendFromGSIndex(SDValue Extend,
// We have indexed loads for all legal index types. Indices are always
// zero extended
return Extend.getOpcode() == ISD::ZERO_EXTEND &&
- isTypeLegal(Extend.getValueType()) &&
- isTypeLegal(Extend.getOperand(0).getValueType());
+ isTypeLegal(Extend.getValueType()) &&
+ isTypeLegal(Extend.getOperand(0).getValueType()) &&
+ Extend.getOperand(0).getValueType().getVectorElementType() != MVT::i1;
}
bool RISCVTargetLowering::shouldConvertFpToSat(unsigned Op, EVT FPVT,
diff --git a/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
index 07dcddd9c68601..f3ae03af7c7868 100644
--- a/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
@@ -2153,3 +2153,19 @@ define <vscale x 32 x i8> @mgather_baseidx_nxv32i8(ptr %base, <vscale x 32 x i8>
%v = call <vscale x 32 x i8> @llvm.masked.gather.nxv32i8.nxv32p0(<vscale x 32 x ptr> %ptrs, i32 2, <vscale x 32 x i1> %m, <vscale x 32 x i8> %passthru)
ret <vscale x 32 x i8> %v
}
+
+define <vscale x 1 x i8> @mgather_baseidx_zext_nxv1i1_nxv1i8(ptr %base, <vscale x 1 x i1> %idxs, <vscale x 1 x i1> %m, <vscale x 1 x i8> %passthru) {
+; CHECK-LABEL: mgather_baseidx_zext_nxv1i1_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vluxei8.v v9, (a0), v10, v0.t
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %eidxs = zext <vscale x 1 x i1> %idxs to <vscale x 1 x i8>
+ %ptrs = getelementptr inbounds i8, ptr %base, <vscale x 1 x i8> %eidxs
+ %v = call <vscale x 1 x i8> @llvm.masked.gather.nxv1i8.nxv1p0(<vscale x 1 x ptr> %ptrs, i32 1, <vscale x 1 x i1> %m, <vscale x 1 x i8> %passthru)
+ ret <vscale x 1 x i8> %v
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
index dc67c64f3ffda8..652e7a128a9606 100644
--- a/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
@@ -1831,3 +1831,18 @@ define void @mscatter_baseidx_nxv16i16_nxv16f64(<vscale x 8 x double> %val0, <vs
call void @llvm.masked.scatter.nxv16f64.nxv16p0(<vscale x 16 x double> %v1, <vscale x 16 x ptr> %ptrs, i32 8, <vscale x 16 x i1> %m)
ret void
}
+
+define void @mscatter_baseidx_zext_nxv1i1_nxv1i8(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i1> %idxs, <vscale x 1 x i1> %m) {
+; CHECK-LABEL: mscatter_baseidx_zext_nxv1i1_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vsoxei8.v v8, (a0), v10, v0.t
+; CHECK-NEXT: ret
+ %eidxs = zext <vscale x 1 x i1> %idxs to <vscale x 1 x i8>
+ %ptrs = getelementptr inbounds i8, ptr %base, <vscale x 1 x i8> %eidxs
+ call void @llvm.masked.scatter.nxv1i8.nxv1p0(<vscale x 1 x i8> %val, <vscale x 1 x ptr> %ptrs, i32 1, <vscale x 1 x i1> %m)
+ ret void
+}
|
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LGTM.
@@ -20043,8 +20043,9 @@ bool RISCVTargetLowering::shouldRemoveExtendFromGSIndex(SDValue Extend, | |||
// We have indexed loads for all legal index types. Indices are always |
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Oh, we need reword these comments.
i1 is a legal type, but isn't valid for indexed loads and stores. Fixes llvm#83929 Co-authored-by: Craig Topper <craig.topper@sifive.com>
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LGTM
i1 is a legal type, but isn't valid for indexed loads and stores.
Fixes #83929