[AMDGPU] Use BUF multiclasses to reduce repetition. NFC. #84003
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Define BUF Real instructions with this general pattern for all
architectures (not just GFX11):
multiclass Something_Real_gfx11<...> {
defvar ps = !cast<Pseudo>(NAME);
def _gfx11 : ...;
}
This allows removing a huge amount of repetition in the definitions of
individual Real instructions, where they would have to !cast their own
name to a Pseudo and pass that in as a class argument.
jayfoad
requested review from
kosarev,
Sisyph,
rampitec,
piotrAMD and
mbrkusanin
|
@llvm/pr-subscribers-backend-amdgpu Author: Jay Foad (jayfoad) ChangesDefine BUF Real instructions with this general pattern for all multiclass Something_Real_gfx11<...> { This allows removing a huge amount of repetition in the definitions of Patch is 36.17 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/84003.diff 1 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td
index a8af95422085e2..cb68e45d69e8d2 100644
--- a/llvm/lib/Target/AMDGPU/BUFInstructions.td
+++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td
@@ -2323,19 +2323,41 @@ class Base_MUBUF_Real_gfx6_gfx7_gfx10<bits<7> op, MUBUF_Pseudo ps, int ef> :
let Inst{55} = ps.tfe;
}
-class MUBUF_Real_gfx10<bits<8> op, MUBUF_Pseudo ps> :
- Base_MUBUF_Real_gfx6_gfx7_gfx10<op{6-0}, ps, SIEncodingFamily.GFX10> {
- let Inst{15} = !if(ps.has_dlc, cpol{CPolBit.DLC}, ps.dlc_value);
- let Inst{25} = op{7};
- let AssemblerPredicate = isGFX10Only;
- let DecoderNamespace = "GFX10";
+multiclass MUBUF_Real_gfx10<bits<8> op> {
+ defvar ps = !cast<MUBUF_Pseudo>(NAME);
+ def _gfx10 : Base_MUBUF_Real_gfx6_gfx7_gfx10<op{6-0}, ps, SIEncodingFamily.GFX10> {
+ let Inst{15} = !if(ps.has_dlc, cpol{CPolBit.DLC}, ps.dlc_value);
+ let Inst{25} = op{7};
+ let AssemblerPredicate = isGFX10Only;
+ let DecoderNamespace = "GFX10";
+ }
+}
+
+multiclass MUBUF_Real_gfx6_gfx7<bits<8> op> {
+ defvar ps = !cast<MUBUF_Pseudo>(NAME);
+ def _gfx6_gfx7 : Base_MUBUF_Real_gfx6_gfx7_gfx10<op{6-0}, ps, SIEncodingFamily.SI> {
+ let Inst{15} = ps.addr64;
+ let AssemblerPredicate = isGFX6GFX7;
+ let DecoderNamespace = "GFX6GFX7";
+ }
+}
+
+multiclass MUBUF_Real_gfx6<bits<8> op> {
+ defvar ps = !cast<MUBUF_Pseudo>(NAME);
+ def _gfx6 : Base_MUBUF_Real_gfx6_gfx7_gfx10<op{6-0}, ps, SIEncodingFamily.SI> {
+ let Inst{15} = ps.addr64;
+ let AssemblerPredicate = isGFX6;
+ let DecoderNamespace = "GFX6";
+ }
}
-class MUBUF_Real_gfx6_gfx7<bits<8> op, MUBUF_Pseudo ps> :
- Base_MUBUF_Real_gfx6_gfx7_gfx10<op{6-0}, ps, SIEncodingFamily.SI> {
- let Inst{15} = ps.addr64;
- let AssemblerPredicate = isGFX6GFX7;
- let DecoderNamespace = "GFX6GFX7";
+multiclass MUBUF_Real_gfx7<bits<8> op> {
+ defvar ps = !cast<MUBUF_Pseudo>(NAME);
+ def _gfx7 : Base_MUBUF_Real_gfx6_gfx7_gfx10<op{6-0}, ps, SIEncodingFamily.SI> {
+ let Inst{15} = ps.addr64;
+ let AssemblerPredicate = isGFX7Only;
+ let DecoderNamespace = "GFX7";
+ }
}
//===----------------------------------------------------------------------===//
@@ -2407,19 +2429,19 @@ class VBUFFER_MUBUF_Real_gfx12<bits<8> op, MUBUF_Pseudo ps,
let DecoderNamespace = "GFX12";
}
-class VBUFFER_MTBUF_Real_gfx12<bits<4> op, MTBUF_Pseudo ps,
- string real_name = ps.Mnemonic> :
- VBUFFER_Real<ps, real_name>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.GFX12> {
+multiclass VBUFFER_MTBUF_Real_gfx12<bits<4> op, string real_name> {
+ defvar ps = !cast<MTBUF_Pseudo>(NAME);
+ def _gfx12 : VBUFFER_Real<ps, real_name>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.GFX12> {
+ let MTBUF = 1;
- let MTBUF = 1;
-
- bits<7> format;
+ bits<7> format;
- let Inst{17-14} = op;
- let Inst{21-18} = 0b1000;
- let Inst{61-55} = format;
- let AssemblerPredicate = isGFX12Only;
- let DecoderNamespace = "GFX12";
+ let Inst{17-14} = op;
+ let Inst{21-18} = 0b1000;
+ let Inst{61-55} = format;
+ let AssemblerPredicate = isGFX12Only;
+ let DecoderNamespace = "GFX12";
+ }
}
//===----------------------------------------------------------------------===//
@@ -2442,24 +2464,26 @@ class Mnem_gfx11 <string mnemonic, string real_name> :
class Mnem_gfx12 <string mnemonic, string real_name> :
MnemonicAlias<mnemonic, real_name>, Requires<[isGFX12Plus]>;
-class MUBUF_Real_gfx11_impl<bits<8> op, string ps_name, string real_name> :
- MUBUF_Real_gfx11<op, !cast<MUBUF_Pseudo>(ps_name), real_name>;
+multiclass MUBUF_Real_gfx11_impl<bits<8> op, string real_name> {
+ def _gfx11 : MUBUF_Real_gfx11<op, !cast<MUBUF_Pseudo>(NAME), real_name>;
+}
-class VBUFFER_MUBUF_Real_gfx12_impl<bits<8> op, string ps_name, string real_name> :
- VBUFFER_MUBUF_Real_gfx12<op, !cast<MUBUF_Pseudo>(ps_name), real_name>;
+multiclass VBUFFER_MUBUF_Real_gfx12_impl<bits<8> op, string real_name> {
+ def _gfx12 : VBUFFER_MUBUF_Real_gfx12<op, !cast<MUBUF_Pseudo>(NAME), real_name>;
+}
multiclass MUBUF_Real_AllAddr_gfx11_Renamed_Impl2<bits<8> op, string real_name> {
- def _BOTHEN_gfx11 : MUBUF_Real_gfx11_impl<op, NAME # "_BOTHEN", real_name>;
- def _IDXEN_gfx11 : MUBUF_Real_gfx11_impl<op, NAME # "_IDXEN", real_name>;
- def _OFFEN_gfx11 : MUBUF_Real_gfx11_impl<op, NAME # "_OFFEN", real_name>;
- def _OFFSET_gfx11 : MUBUF_Real_gfx11_impl<op, NAME # "_OFFSET", real_name>;
+ defm _BOTHEN : MUBUF_Real_gfx11_impl<op, real_name>;
+ defm _IDXEN : MUBUF_Real_gfx11_impl<op, real_name>;
+ defm _OFFEN : MUBUF_Real_gfx11_impl<op, real_name>;
+ defm _OFFSET : MUBUF_Real_gfx11_impl<op, real_name>;
}
multiclass MUBUF_Real_AllAddr_gfx12_Renamed_Impl2<bits<8> op, string real_name> {
- def _BOTHEN_gfx12 : VBUFFER_MUBUF_Real_gfx12_impl<op, NAME # "_VBUFFER_BOTHEN", real_name>;
- def _IDXEN_gfx12 : VBUFFER_MUBUF_Real_gfx12_impl<op, NAME # "_VBUFFER_IDXEN", real_name>;
- def _OFFEN_gfx12 : VBUFFER_MUBUF_Real_gfx12_impl<op, NAME # "_VBUFFER_OFFEN", real_name>;
- def _OFFSET_gfx12 : VBUFFER_MUBUF_Real_gfx12_impl<op, NAME # "_VBUFFER_OFFSET", real_name>;
+ defm _VBUFFER_BOTHEN : VBUFFER_MUBUF_Real_gfx12_impl<op, real_name>;
+ defm _VBUFFER_IDXEN : VBUFFER_MUBUF_Real_gfx12_impl<op, real_name>;
+ defm _VBUFFER_OFFEN : VBUFFER_MUBUF_Real_gfx12_impl<op, real_name>;
+ defm _VBUFFER_OFFSET : VBUFFER_MUBUF_Real_gfx12_impl<op, real_name>;
}
multiclass MUBUF_Real_AllAddr_gfx11_gfx12_Renamed_Impl2<bits<8> op, string real_name> :
@@ -2492,38 +2516,30 @@ multiclass MUBUF_Real_AllAddr_gfx11_gfx12_Renamed<bits<8> op, string real_name>
def : Mnem_gfx11_gfx12<get_BUF_ps<NAME>.Mnemonic, real_name>;
}
-class MUBUF_Real_Atomic_gfx11_impl<bits<8> op, string ps_name,
- string real_name> :
- MUBUF_Real_gfx11<op, !cast<MUBUF_Pseudo>(ps_name), real_name>;
+multiclass MUBUF_Real_Atomic_gfx11_impl<bits<8> op, string real_name> {
+ def _gfx11 : MUBUF_Real_gfx11<op, !cast<MUBUF_Pseudo>(NAME), real_name>;
+}
-class MUBUF_Real_Atomic_gfx12_impl<bits<8> op, string ps_name,
- string real_name> :
- VBUFFER_MUBUF_Real_gfx12<op, !cast<MUBUF_Pseudo>(ps_name), real_name>;
+multiclass MUBUF_Real_Atomic_gfx12_impl<bits<8> op, string real_name> {
+ def _gfx12 : VBUFFER_MUBUF_Real_gfx12<op, !cast<MUBUF_Pseudo>(NAME), real_name>;
+}
multiclass MUBUF_Real_Atomic_gfx11_Renamed_impl<bits<8> op, bit is_return,
string real_name> {
defvar Rtn = !if(is_return, "_RTN", "");
- def _BOTHEN#Rtn#_gfx11 :
- MUBUF_Real_Atomic_gfx11_impl<op, NAME # "_BOTHEN" # Rtn, real_name>;
- def _IDXEN#Rtn#_gfx11 :
- MUBUF_Real_Atomic_gfx11_impl<op, NAME # "_IDXEN" # Rtn, real_name>;
- def _OFFEN#Rtn#_gfx11 :
- MUBUF_Real_Atomic_gfx11_impl<op, NAME # "_OFFEN" # Rtn, real_name>;
- def _OFFSET#Rtn#_gfx11 :
- MUBUF_Real_Atomic_gfx11_impl<op, NAME # "_OFFSET" # Rtn, real_name>;
+ defm _BOTHEN#Rtn : MUBUF_Real_Atomic_gfx11_impl<op, real_name>;
+ defm _IDXEN#Rtn : MUBUF_Real_Atomic_gfx11_impl<op, real_name>;
+ defm _OFFEN#Rtn : MUBUF_Real_Atomic_gfx11_impl<op, real_name>;
+ defm _OFFSET#Rtn : MUBUF_Real_Atomic_gfx11_impl<op, real_name>;
}
multiclass MUBUF_Real_Atomic_gfx12_Renamed_impl<bits<8> op, bit is_return,
string real_name> {
defvar Rtn = !if(is_return, "_RTN", "");
- def _BOTHEN#Rtn#_gfx12 :
- MUBUF_Real_Atomic_gfx12_impl<op, NAME # "_VBUFFER_BOTHEN" # Rtn, real_name>;
- def _IDXEN#Rtn#_gfx12 :
- MUBUF_Real_Atomic_gfx12_impl<op, NAME # "_VBUFFER_IDXEN" # Rtn, real_name>;
- def _OFFEN#Rtn#_gfx12 :
- MUBUF_Real_Atomic_gfx12_impl<op, NAME # "_VBUFFER_OFFEN" # Rtn, real_name>;
- def _OFFSET#Rtn#_gfx12 :
- MUBUF_Real_Atomic_gfx12_impl<op, NAME # "_VBUFFER_OFFSET" # Rtn, real_name>;
+ defm _VBUFFER_BOTHEN#Rtn : MUBUF_Real_Atomic_gfx12_impl<op, real_name>;
+ defm _VBUFFER_IDXEN#Rtn : MUBUF_Real_Atomic_gfx12_impl<op, real_name>;
+ defm _VBUFFER_OFFEN#Rtn : MUBUF_Real_Atomic_gfx12_impl<op, real_name>;
+ defm _VBUFFER_OFFSET#Rtn : MUBUF_Real_Atomic_gfx12_impl<op, real_name>;
}
multiclass MUBUF_Real_Atomic_gfx11_gfx12_Renamed_impl<bits<8> op, bit is_return,
@@ -2652,52 +2668,40 @@ defm BUFFER_ATOMIC_PK_ADD_BF16 : MUBUF_Real_Atomic_gfx12<0x05a>;
//===----------------------------------------------------------------------===//
multiclass MUBUF_Real_AllAddr_Helper_gfx10<bits<8> op> {
- def _BOTHEN_gfx10 :
- MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>;
- def _IDXEN_gfx10 :
- MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>;
- def _OFFEN_gfx10 :
- MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>;
- def _OFFSET_gfx10 :
- MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>;
+ defm _BOTHEN : MUBUF_Real_gfx10<op>;
+ defm _IDXEN : MUBUF_Real_gfx10<op>;
+ defm _OFFEN : MUBUF_Real_gfx10<op>;
+ defm _OFFSET : MUBUF_Real_gfx10<op>;
}
multiclass MUBUF_Real_AllAddr_gfx10<bits<8> op> {
defm NAME : MUBUF_Real_AllAddr_Helper_gfx10<op>;
defm _TFE : MUBUF_Real_AllAddr_Helper_gfx10<op>;
}
multiclass MUBUF_Real_AllAddr_Lds_gfx10<bits<8> op, bit isTFE = 0> {
- def _OFFSET_gfx10 : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>;
- def _OFFEN_gfx10 : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>;
- def _IDXEN_gfx10 : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>;
- def _BOTHEN_gfx10 : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>;
+ defm _OFFSET : MUBUF_Real_gfx10<op>;
+ defm _OFFEN : MUBUF_Real_gfx10<op>;
+ defm _IDXEN : MUBUF_Real_gfx10<op>;
+ defm _BOTHEN : MUBUF_Real_gfx10<op>;
if !not(isTFE) then {
- def _LDS_OFFSET_gfx10 : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFSET")>;
- def _LDS_OFFEN_gfx10 : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFEN")>;
- def _LDS_IDXEN_gfx10 : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_LDS_IDXEN")>;
- def _LDS_BOTHEN_gfx10 : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_LDS_BOTHEN")>;
+ defm _LDS_OFFSET : MUBUF_Real_gfx10<op>;
+ defm _LDS_OFFEN : MUBUF_Real_gfx10<op>;
+ defm _LDS_IDXEN : MUBUF_Real_gfx10<op>;
+ defm _LDS_BOTHEN : MUBUF_Real_gfx10<op>;
}
}
multiclass MUBUF_Real_Atomics_RTN_gfx10<bits<8> op> {
- def _BOTHEN_RTN_gfx10 :
- MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN_RTN")>;
- def _IDXEN_RTN_gfx10 :
- MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN_RTN")>;
- def _OFFEN_RTN_gfx10 :
- MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN_RTN")>;
- def _OFFSET_RTN_gfx10 :
- MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET_RTN")>;
+ defm _BOTHEN_RTN : MUBUF_Real_gfx10<op>;
+ defm _IDXEN_RTN : MUBUF_Real_gfx10<op>;
+ defm _OFFEN_RTN : MUBUF_Real_gfx10<op>;
+ defm _OFFSET_RTN : MUBUF_Real_gfx10<op>;
}
multiclass MUBUF_Real_Atomics_gfx10<bits<8> op> :
MUBUF_Real_Atomics_RTN_gfx10<op> {
- def _BOTHEN_gfx10 :
- MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>;
- def _IDXEN_gfx10 :
- MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>;
- def _OFFEN_gfx10 :
- MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>;
- def _OFFSET_gfx10 :
- MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>;
+ defm _BOTHEN : MUBUF_Real_gfx10<op>;
+ defm _IDXEN : MUBUF_Real_gfx10<op>;
+ defm _OFFEN : MUBUF_Real_gfx10<op>;
+ defm _OFFSET : MUBUF_Real_gfx10<op>;
}
defm BUFFER_STORE_BYTE_D16_HI : MUBUF_Real_AllAddr_gfx10<0x019>;
@@ -2720,78 +2724,51 @@ defm BUFFER_STORE_FORMAT_D16_XY : MUBUF_Real_AllAddr_gfx10<0x085>;
defm BUFFER_STORE_FORMAT_D16_XYZ : MUBUF_Real_AllAddr_gfx10<0x086>;
defm BUFFER_STORE_FORMAT_D16_XYZW : MUBUF_Real_AllAddr_gfx10<0x087>;
-def BUFFER_GL0_INV_gfx10 :
- MUBUF_Real_gfx10<0x071, BUFFER_GL0_INV>;
-def BUFFER_GL1_INV_gfx10 :
- MUBUF_Real_gfx10<0x072, BUFFER_GL1_INV>;
+defm BUFFER_GL0_INV : MUBUF_Real_gfx10<0x071>;
+defm BUFFER_GL1_INV : MUBUF_Real_gfx10<0x072>;
//===----------------------------------------------------------------------===//
// MUBUF - GFX6, GFX7, GFX10.
//===----------------------------------------------------------------------===//
-multiclass MUBUF_Real_gfx6<bits<8> op> {
- let AssemblerPredicate = isGFX6, DecoderNamespace = "GFX6" in
- def _gfx6 : MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME)>;
-}
-
-multiclass MUBUF_Real_gfx7<bits<8> op> {
- let AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" in
- def _gfx7 : MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME)>;
-}
-
multiclass MUBUF_Real_AllAddr_Helper_gfx6_gfx7<bits<8> op> {
- def _ADDR64_gfx6_gfx7 :
- MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_ADDR64")>;
- def _BOTHEN_gfx6_gfx7 :
- MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>;
- def _IDXEN_gfx6_gfx7 :
- MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>;
- def _OFFEN_gfx6_gfx7 :
- MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>;
- def _OFFSET_gfx6_gfx7 :
- MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>;
+ defm _ADDR64 : MUBUF_Real_gfx6_gfx7<op>;
+ defm _BOTHEN : MUBUF_Real_gfx6_gfx7<op>;
+ defm _IDXEN : MUBUF_Real_gfx6_gfx7<op>;
+ defm _OFFEN : MUBUF_Real_gfx6_gfx7<op>;
+ defm _OFFSET : MUBUF_Real_gfx6_gfx7<op>;
}
multiclass MUBUF_Real_AllAddr_gfx6_gfx7<bits<8> op> {
defm NAME : MUBUF_Real_AllAddr_Helper_gfx6_gfx7<op>;
defm _TFE : MUBUF_Real_AllAddr_Helper_gfx6_gfx7<op>;
}
multiclass MUBUF_Real_AllAddr_Lds_gfx6_gfx7<bits<8> op, bit isTFE = 0> {
- def _OFFSET_gfx6_gfx7 : MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>;
- def _ADDR64_gfx6_gfx7 : MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_ADDR64")>;
- def _OFFEN_gfx6_gfx7 : MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>;
- def _IDXEN_gfx6_gfx7 : MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>;
- def _BOTHEN_gfx6_gfx7 : MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>;
+ defm _OFFSET : MUBUF_Real_gfx6_gfx7<op>;
+ defm _ADDR64 : MUBUF_Real_gfx6_gfx7<op>;
+ defm _OFFEN : MUBUF_Real_gfx6_gfx7<op>;
+ defm _IDXEN : MUBUF_Real_gfx6_gfx7<op>;
+ defm _BOTHEN : MUBUF_Real_gfx6_gfx7<op>;
if !not(isTFE) then {
- def _LDS_OFFSET_gfx6_gfx7 : MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFSET")>;
- def _LDS_ADDR64_gfx6_gfx7 : MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_LDS_ADDR64")>;
- def _LDS_OFFEN_gfx6_gfx7 : MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFEN")>;
- def _LDS_IDXEN_gfx6_gfx7 : MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_LDS_IDXEN")>;
- def _LDS_BOTHEN_gfx6_gfx7 : MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_LDS_BOTHEN")>;
+ defm _LDS_OFFSET : MUBUF_Real_gfx6_gfx7<op>;
+ defm _LDS_ADDR64 : MUBUF_Real_gfx6_gfx7<op>;
+ defm _LDS_OFFEN : MUBUF_Real_gfx6_gfx7<op>;
+ defm _LDS_IDXEN : MUBUF_Real_gfx6_gfx7<op>;
+ defm _LDS_BOTHEN : MUBUF_Real_gfx6_gfx7<op>;
}
}
multiclass MUBUF_Real_Atomics_gfx6_gfx7<bits<8> op> {
- def _ADDR64_gfx6_gfx7 :
- MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_ADDR64")>;
- def _BOTHEN_gfx6_gfx7 :
- MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>;
- def _IDXEN_gfx6_gfx7 :
- MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>;
- def _OFFEN_gfx6_gfx7 :
- MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>;
- def _OFFSET_gfx6_gfx7 :
- MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>;
-
- def _ADDR64_RTN_gfx6_gfx7 :
- MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_ADDR64_RTN")>;
- def _BOTHEN_RTN_gfx6_gfx7 :
- MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN_RTN")>;
- def _IDXEN_RTN_gfx6_gfx7 :
- MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN_RTN")>;
- def _OFFEN_RTN_gfx6_gfx7 :
- MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN_RTN")>;
- def _OFFSET_RTN_gfx6_gfx7 :
- MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET_RTN")>;
+ defm _ADDR64 : MUBUF_Real_gfx6_gfx7<op>;
+ defm _BOTHEN : MUBUF_Real_gfx6_gfx7<op>;
+ defm _IDXEN : MUBUF_Real_gfx6_gfx7<op>;
+ defm _OFFEN : MUBUF_Real_gfx6_gfx7<op>;
+ defm _OFFSET : MUBUF_Real_gfx6_gfx7<op>;
+
+ defm _ADDR64_RTN : MUBUF_Real_gfx6_gfx7<op>;
+ defm _BOTHEN_RTN : MUBUF_Real_gfx6_gfx7<op>;
+ defm _IDXEN_RTN : MUBUF_Real_gfx6_gfx7<op>;
+ defm _OFFEN_RTN : MUBUF_Real_gfx6_gfx7<op>;
+ defm _OFFSET_RTN : MUBUF_Real_gfx6_gfx7<op>;
}
multiclass MUBUF_Real_AllAddr_gfx6_gfx7_gfx10<bits<8> op> :
@@ -2874,7 +2851,7 @@ defm BUFFER_ATOMIC_CSUB : MUBUF_Real_Atomics_gfx10<0x034>;
defm BUFFER_WBINVL1_SC : MUBUF_Real_gfx6<0x070>;
defm BUFFER_WBINVL1_VOL : MUBUF_Real_gfx7<0x070>;
-def BUFFER_WBINVL1_gfx6_gfx7 : MUBUF_Real_gfx6_gfx7<0x071, BUFFER_WBINVL1>;
+defm BUFFER_WBINVL1 : MUBUF_Real_gfx6_gfx7<0x071>;
//===----------------------------------------------------------------------===//
// Base ENC_MTBUF for GFX6, GFX7, GFX10, GFX11.
@@ -2892,18 +2869,19 @@ class Base_MTBUF_Real_gfx6_gfx7_gfx10_gfx11<MTBUF_Pseudo ps, int ef,
let Inst{63-56} = !if(ps.has_soffset, soffset, ?);
}
-class MTBUF_Real_gfx11<bits<4> op, MTBUF_Pseudo ps,
- string real_name = ps.Mnemonic> :
- Base_MTBUF_Real_gfx6_gfx7_gfx10_gfx11<ps, SIEncodingFamily.GFX11, real_name> {
- let Inst{12} = !if(ps.has_slc, cpol{CPolBit.SLC}, ?);
- let Inst{13} = !if(ps.has_dlc, cpol{CPolBit.DLC}, ps.dlc_value);
- let Inst{18-15} = op;
- let Inst{25-19} = format;
- let Inst{53} = ps.tfe;
- let Inst{54} = ps.offen;
- let Inst{55} = ps.idxen;
- let AssemblerPredicate = isGFX11Only;
- let DecoderNamespace = "GFX11";
+multiclass MTBUF_Real_gfx11<bits<4> op, string real_name> {
+ defvar ps = !cast<MTBUF_Pseudo>(NAME);
+ def _gfx11 : Base_MTBUF_Real_gfx6_gfx7_gfx10_gfx11<ps, SIEncodingFamily.GFX11, real_name> {
+ let Inst{12} = !if(ps.has_slc, cpol{CPolBit.SLC}, ?);
+ let Inst{13} = !if(ps.has_dlc, cpol{CPolBit.DLC}, ps.dlc_value);
+ let Inst{18-15} = op;
+ let Inst{25-19} = format;
+ let Inst{53} = ps.tfe;
+ let Inst{54} = ps.offen;
+ let Inst{55} = ps.idxen;
+ let AssemblerPredicate = isGFX11Only;
+ let DecoderNamespace = "GFX11";
+ }
}
class Base_MTBUF_Real_gfx6_gfx7_gfx10<bits<3> op, MTBUF_Pseudo ps, int ef> :
@@ -2920,23 +2898,15 @@ class Base_MTBUF_Real_gfx6_gfx7_gfx10<bits<3> op, MTBUF_Pseudo ps, int ef> :
//===----------------------------------------------------------------------===//
multiclass MTBUF_Real_AllAddr_gfx11_gfx12_Renamed_Impl<bits<4> op, string real_name> {
- def _BOTHEN_gfx11 :
- MTBUF_Real_gfx11<op, !cast<MTBUF_Pseudo>(NAME#"_BOTHEN"), real_name>;
- def _IDXEN_gfx11 :
- MTBUF_Real_gfx11<op, !cast<MTBUF_Pseudo>(NAME#"_IDXEN"), real_name>;
- def _OFFEN_gfx11 :
- MTBUF_Real_gfx11<op, !cast<MTBUF_Pseudo>(NAME#"_OFFEN"), real_name>;
- def _OFFSET_gfx11 :
- MTBUF_Real_gfx11<op, !cast<MTBUF_Pseudo>(NAME#"_OFFSET"), real_name>;
-
- def _BOTHEN_gfx12 :
- VBUFFER_MTBUF_Real_gfx12<op, !cast<MTBUF_Pseudo>(NAME#"_VBUFFER_BOTHEN"), real_name>;
- def _IDXEN_gfx12 :
- VBUFFER_MTBUF_Real_gfx12<op, !cast<MTBUF_Pseudo>(NAME#"_VBUFFER_IDXEN"), real_name>;
- def _OFFEN_gfx12 :
- VBUFFER_MTBUF_Real_gfx12<op, !cast<MTBUF_Pseudo>(NAME#"_VBUFFER_OFFEN"), real_name>;
- def _OFFSET_gfx12 :
- VBUFFER_MTBUF_Real_gfx12<op, !cast<MTBUF_Pseudo>(NAME#"_VBUFFER_OFFSET"), real_name>;
+ defm _BOTHEN : MTBUF_Real_gfx11<op, real_name>;
+ defm _IDXEN : MTBUF_Real_gfx11<op, real_name>;
+ defm _OFFEN : MTBUF_Real_gfx11<op, real_name>;
+ defm _OFFSET : MTBUF_Real_gfx11<op, real_name>;
+
+ defm _VBUFFER_BOTHEN : VBUFFER_MTBUF_Real_gfx12<op, real_name>;
+ defm _VBUFFER_IDXEN : VBUFFER_MTBUF_Real_gfx12<op, real_name>;
+ defm _VBUFFER_OFFEN : VBUFFER_MTBUF_Real_gfx12<op, real_name>;
+ defm _VBUFFER_OFFSET : VBUFFER_MTBUF_Real_gfx12<op, real_name>;
}
multiclass MTBUF_Real_AllAddr_gfx11_gfx12<bits<4> op>
@@ -2970,24 +2940,22 @@ defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Real_AllAddr_gfx11_gfx12<0x007>;
// MTBUF - GFX10.
//===----------------------------------------------------------------------===//
-class MTBUF_Real_gfx10<bits<4> op, MTBUF_Pseudo ps> :
- Base_MTBUF_Real_gfx6_gfx7_gfx10<op{2-0}, ps, SIEncodingFamily.GFX1...
[truncated]
|
kosarev
approved these changes
Mar 5, 2024
jayfoad
changed the title
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Define BUF Real instructions with this general pattern for all
architectures (not just GFX11):
multiclass Something_Real_gfx11<...> {
defvar ps = !cast(NAME);
def _gfx11 : ...;
}
This allows removing a huge amount of repetition in the definitions of
individual Real instructions, where they would have to !cast their own
name to a Pseudo and pass that in as a class argument.