[AArch64][GlobalISel] Avoid generating inserts for undefs when selecting G_BUILD_VECTOR #84452
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@llvm/pr-subscribers-backend-aarch64 @llvm/pr-subscribers-llvm-globalisel Author: Dhruv Chawla (work) (dc03-work) ChangesIt is safe to ignore undef values when selecting G_BUILD_VECTOR as undef values choose random registers for copying values from. Patch is 133.93 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/84452.diff 40 Files Affected:
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 77d6e7e93fb009..bdb916afee7a88 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -5929,9 +5929,12 @@ bool AArch64InstructionSelector::selectBuildVector(MachineInstr &I,
for (unsigned i = 2, e = DstSize / EltSize + 1; i < e; ++i) {
// Note that if we don't do a subregister copy, we can end up making an
// extra register.
- PrevMI = &*emitLaneInsert(std::nullopt, DstVec, I.getOperand(i).getReg(),
- i - 1, RB, MIB);
- DstVec = PrevMI->getOperand(0).getReg();
+ Register OpReg = I.getOperand(i).getReg();
+ // Do not emit inserts for undefs
+ if (!getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, OpReg, MRI)) {
+ PrevMI = &*emitLaneInsert(std::nullopt, DstVec, OpReg, i - 1, RB, MIB);
+ DstVec = PrevMI->getOperand(0).getReg();
+ }
}
// If DstTy's size in bits is less than 128, then emit a subregister copy
@@ -5963,12 +5966,20 @@ bool AArch64InstructionSelector::selectBuildVector(MachineInstr &I,
MachineOperand &RegOp = I.getOperand(1);
RegOp.setReg(Reg);
RBI.constrainGenericRegister(DstReg, *RC, MRI);
- } else {
+ } else if (PrevMI) {
// We don't need a subregister copy. Save a copy by re-using the
// destination register on the final insert.
- assert(PrevMI && "PrevMI was null?");
PrevMI->getOperand(0).setReg(I.getOperand(0).getReg());
constrainSelectedInstRegOperands(*PrevMI, TII, TRI, RBI);
+ } else {
+ // All the operands (other than the first one) to the G_BUILD_VECTOR were
+ // undef, so PrevMI is nullptr. Emit a copy from the vector made from the
+ // first operand to the destination register.
+ const TargetRegisterClass *RC =
+ getRegClassForTypeOnBank(DstTy, *RBI.getRegBank(DstVec, MRI, TRI));
+ Register DstReg = I.getOperand(0).getReg();
+ MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {}).addReg(DstVec, 0);
+ RBI.constrainGenericRegister(DstReg, *RC, MRI);
}
I.eraseFromParent();
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir
index 5de97256fc85a3..9e3f65cbe218d1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir
@@ -266,13 +266,9 @@ body: |
; CHECK-LABEL: name: undef_elts_different_regbanks
; CHECK: liveins: $w0
; CHECK: %val:gpr32all = COPY $w0
- ; CHECK: %undef:gpr32 = IMPLICIT_DEF
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %val, %subreg.ssub
- ; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, %undef
- ; CHECK: [[INSvi32gpr1:%[0-9]+]]:fpr128 = INSvi32gpr [[INSvi32gpr]], 2, %undef
- ; CHECK: %bv:fpr128 = INSvi32gpr [[INSvi32gpr1]], 3, %undef
- ; CHECK: $q0 = COPY %bv
+ ; CHECK: $q0 = COPY [[INSERT_SUBREG]]
; CHECK: RET_ReallyLR implicit $q0
%val:gpr(s32) = COPY $w0
%undef:gpr(s32) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir
index 6e01723f49935d..5f280ae2e3024e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir
@@ -19,20 +19,18 @@ body: |
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
- ; CHECK: [[DEF1:%[0-9]+]]:gpr32 = IMPLICIT_DEF
- ; CHECK: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
- ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[DEF]], %subreg.ssub
- ; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[DEF1]]
- ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
+ ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[DEF]], %subreg.ssub
+ ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[INSERT_SUBREG]].dsub
; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
+ ; CHECK: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[COPY]], %subreg.dsub
; CHECK: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
- ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[COPY]], %subreg.dsub
- ; CHECK: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
- ; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[COPY1]], %subreg.dsub
+ ; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[COPY1]], %subreg.dsub
; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG2]], 0
- ; CHECK: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF
- ; CHECK: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[LDRDui]], %subreg.dsub
+ ; CHECK: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[LDRDui]], %subreg.dsub
; CHECK: [[TBLv16i8One:%[0-9]+]]:fpr128 = TBLv16i8One [[INSvi64lane]], [[INSERT_SUBREG3]]
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[TBLv16i8One]].dsub
; CHECK: $d0 = COPY [[COPY2]]
diff --git a/llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll b/llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll
index 273bf559554c9d..f47da47002fbcd 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll
@@ -77,7 +77,6 @@ define <1 x i32> @test_bitf_v1i32(<1 x i32> %A, <1 x i32> %B, <1 x i32> %C) {
; CHECK-GI-NEXT: and w8, w8, w10
; CHECK-GI-NEXT: orr w8, w9, w8
; CHECK-GI-NEXT: fmov s0, w8
-; CHECK-GI-NEXT: mov v0.s[1], w8
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
%neg = xor <1 x i32> %C, <i32 -1>
diff --git a/llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll b/llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
index a92ae39c69724d..5c006508d284fd 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
@@ -79,7 +79,6 @@ define <1 x i32> @test_bit_v1i32(<1 x i32> %A, <1 x i32> %B, <1 x i32> %C) {
; CHECK-GI-NEXT: bic w8, w10, w8
; CHECK-GI-NEXT: orr w8, w9, w8
; CHECK-GI-NEXT: fmov s0, w8
-; CHECK-GI-NEXT: mov v0.s[1], w8
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
%and = and <1 x i32> %C, %B
diff --git a/llvm/test/CodeGen/AArch64/abs.ll b/llvm/test/CodeGen/AArch64/abs.ll
index f2cad6631dc267..e00f70b94e3b42 100644
--- a/llvm/test/CodeGen/AArch64/abs.ll
+++ b/llvm/test/CodeGen/AArch64/abs.ll
@@ -252,7 +252,6 @@ define <1 x i32> @abs_v1i32(<1 x i32> %a){
; CHECK-GI-NEXT: add w8, w8, w9
; CHECK-GI-NEXT: eor w8, w8, w9
; CHECK-GI-NEXT: fmov s0, w8
-; CHECK-GI-NEXT: mov v0.s[1], w8
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
entry:
@@ -308,11 +307,6 @@ define <3 x i8> @abs_v3i8(<3 x i8> %a){
; CHECK-GI-NEXT: mov v0.b[1], v1.b[0]
; CHECK-GI-NEXT: fmov s1, w2
; CHECK-GI-NEXT: mov v0.b[2], v1.b[0]
-; CHECK-GI-NEXT: mov v0.b[3], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[4], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[5], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[6], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[7], v0.b[0]
; CHECK-GI-NEXT: abs v0.8b, v0.8b
; CHECK-GI-NEXT: umov w0, v0.b[0]
; CHECK-GI-NEXT: umov w1, v0.b[1]
diff --git a/llvm/test/CodeGen/AArch64/arm64-dup.ll b/llvm/test/CodeGen/AArch64/arm64-dup.ll
index 2112944cc84793..2bf5419e54830b 100644
--- a/llvm/test/CodeGen/AArch64/arm64-dup.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-dup.ll
@@ -373,11 +373,9 @@ define <4 x i16> @test_build_illegal(<4 x i32> %in) {
;
; CHECK-GI-LABEL: test_build_illegal:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov.h v1[1], v0[0]
; CHECK-GI-NEXT: mov s0, v0[3]
-; CHECK-GI-NEXT: mov.h v1[2], v0[0]
-; CHECK-GI-NEXT: mov.h v1[3], v0[0]
-; CHECK-GI-NEXT: fmov d0, d1
+; CHECK-GI-NEXT: mov.h v0[3], v0[0]
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
%val = extractelement <4 x i32> %in, i32 3
%smallval = trunc i32 %val to i16
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
index cc3d80008143cd..d282bee81827fd 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
@@ -1346,7 +1346,6 @@ define <2 x i32> @scalar_to_vector.v2i32(i32 %a) {
; CHECK-GI-LABEL: scalar_to_vector.v2i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: fmov s0, w0
-; CHECK-GI-NEXT: mov v0.s[1], w8
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
%b = insertelement <2 x i32> undef, i32 %a, i32 0
@@ -1354,33 +1353,19 @@ define <2 x i32> @scalar_to_vector.v2i32(i32 %a) {
}
define <4 x i32> @scalar_to_vector.v4i32(i32 %a) {
-; CHECK-SD-LABEL: scalar_to_vector.v4i32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fmov s0, w0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: scalar_to_vector.v4i32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: fmov s0, w0
-; CHECK-GI-NEXT: mov v0.s[1], w8
-; CHECK-GI-NEXT: mov v0.s[2], w8
-; CHECK-GI-NEXT: mov v0.s[3], w8
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: scalar_to_vector.v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov s0, w0
+; CHECK-NEXT: ret
%b = insertelement <4 x i32> undef, i32 %a, i32 0
ret <4 x i32> %b
}
define <2 x i64> @scalar_to_vector.v2i64(i64 %a) {
-; CHECK-SD-LABEL: scalar_to_vector.v2i64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fmov d0, x0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: scalar_to_vector.v2i64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: fmov d0, x0
-; CHECK-GI-NEXT: mov v0.d[1], x8
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: scalar_to_vector.v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov d0, x0
+; CHECK-NEXT: ret
%b = insertelement <2 x i64> undef, i64 %a, i32 0
ret <2 x i64> %b
}
@@ -1900,14 +1885,6 @@ define <16 x i8> @test_concat_v16i8_v8i8_v16i8(<8 x i8> %x, <16 x i8> %y) #0 {
; CHECK-GI-NEXT: mov v0.b[5], v6.b[0]
; CHECK-GI-NEXT: mov v0.b[6], v7.b[0]
; CHECK-GI-NEXT: mov v0.b[7], v16.b[0]
-; CHECK-GI-NEXT: mov v0.b[8], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[9], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[10], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[11], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[12], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[13], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[14], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[15], v0.b[0]
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
; CHECK-GI-NEXT: ret
entry:
@@ -2123,10 +2100,6 @@ define <8 x i16> @test_concat_v8i16_v4i16_v8i16(<4 x i16> %x, <8 x i16> %y) #0 {
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI131_0]
; CHECK-GI-NEXT: mov v0.h[2], v3.h[0]
; CHECK-GI-NEXT: mov v0.h[3], v4.h[0]
-; CHECK-GI-NEXT: mov v0.h[4], v0.h[0]
-; CHECK-GI-NEXT: mov v0.h[5], v0.h[0]
-; CHECK-GI-NEXT: mov v0.h[6], v0.h[0]
-; CHECK-GI-NEXT: mov v0.h[7], v0.h[0]
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
; CHECK-GI-NEXT: ret
entry:
@@ -2266,8 +2239,6 @@ define <4 x i32> @test_concat_v4i32_v2i32_v4i32(<2 x i32> %x, <4 x i32> %y) #0 {
; CHECK-GI-NEXT: mov s2, v0.s[1]
; CHECK-GI-NEXT: mov v0.s[1], v2.s[0]
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI135_0]
-; CHECK-GI-NEXT: mov v0.s[2], v0.s[0]
-; CHECK-GI-NEXT: mov v0.s[3], v0.s[0]
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
; CHECK-GI-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/bitcast.ll b/llvm/test/CodeGen/AArch64/bitcast.ll
index a5551285f2788d..bccfdb93d786f3 100644
--- a/llvm/test/CodeGen/AArch64/bitcast.ll
+++ b/llvm/test/CodeGen/AArch64/bitcast.ll
@@ -21,7 +21,6 @@ define <4 x i16> @foo1(<2 x i32> %a) {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #58712 // =0xe558
; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: mov v1.s[1], w8
; CHECK-GI-NEXT: zip1 v0.2s, v1.2s, v0.2s
; CHECK-GI-NEXT: rev32 v0.4h, v0.4h
; CHECK-GI-NEXT: ret
@@ -42,7 +41,6 @@ define <4 x i16> @foo2(<2 x i32> %a) {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #712 // =0x2c8
; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: mov v1.s[1], w8
; CHECK-GI-NEXT: zip1 v0.2s, v1.2s, v0.2s
; CHECK-GI-NEXT: rev32 v0.4h, v0.4h
; CHECK-GI-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/bswap.ll b/llvm/test/CodeGen/AArch64/bswap.ll
index 9b065accce9146..f4221accfcbc52 100644
--- a/llvm/test/CodeGen/AArch64/bswap.ll
+++ b/llvm/test/CodeGen/AArch64/bswap.ll
@@ -137,7 +137,6 @@ define <1 x i32> @bswap_v1i32(<1 x i32> %a){
; CHECK-GI-NEXT: fmov w8, s0
; CHECK-GI-NEXT: rev w8, w8
; CHECK-GI-NEXT: fmov s0, w8
-; CHECK-GI-NEXT: mov v0.s[1], w8
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/fabs.ll b/llvm/test/CodeGen/AArch64/fabs.ll
index 7c13b49246d230..de108b0bc2b7a0 100644
--- a/llvm/test/CodeGen/AArch64/fabs.ll
+++ b/llvm/test/CodeGen/AArch64/fabs.ll
@@ -160,21 +160,20 @@ define <7 x half> @fabs_v7f16(<7 x half> %a) {
;
; CHECK-GI-NOFP16-LABEL: fabs_v7f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[5]
-; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v1.h[1], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: fabs v2.4s, v3.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v2.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[5]
+; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[6]
+; CHECK-GI-NOFP16-NEXT: fabs v1.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v2.h[1], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v2.h[2], v4.h[0]
+; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v2.4h
; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[2]
; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[3]
-; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: fabs v1.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-GI-NOFP16-NEXT: fabs v1.4s, v2.4s
; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v3.h[0]
; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v1.4s
; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v4.h[0]
@@ -183,7 +182,6 @@ define <7 x half> @fabs_v7f16(<7 x half> %a) {
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v2.h[0]
; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[7], v0.h[0]
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: fabs_v7f16:
diff --git a/llvm/test/CodeGen/AArch64/faddsub.ll b/llvm/test/CodeGen/AArch64/faddsub.ll
index 31389f5a77d6f7..3fade0fc98250f 100644
--- a/llvm/test/CodeGen/AArch64/faddsub.ll
+++ b/llvm/test/CodeGen/AArch64/faddsub.ll
@@ -232,26 +232,24 @@ define <7 x half> @fadd_v7f16(<7 x half> %a, <7 x half> %b) {
;
; CHECK-GI-NOFP16-LABEL: fadd_v7f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[5]
-; CHECK-GI-NOFP16-NEXT: mov h4, v1.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h5, v1.h[5]
-; CHECK-GI-NOFP16-NEXT: fcvtl v6.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl v7.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[6]
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v1.4h
+; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[5]
+; CHECK-GI-NOFP16-NEXT: mov h6, v1.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h7, v1.h[5]
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v2.h[1], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: fadd v2.4s, v2.4s, v3.4s
+; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[6]
; CHECK-GI-NOFP16-NEXT: mov v4.h[1], v5.h[0]
-; CHECK-GI-NOFP16-NEXT: fadd v3.4s, v6.4s, v7.4s
-; CHECK-GI-NOFP16-NEXT: mov v2.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v4.h[2], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v3.4s
-; CHECK-GI-NOFP16-NEXT: mov v2.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v4.h[3], v0.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v6.h[1], v7.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v2.4s
+; CHECK-GI-NOFP16-NEXT: mov v4.h[2], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v6.h[2], v1.h[0]
; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[3]
-; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v2.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v4.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v4.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v6.4h
; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
; CHECK-GI-NOFP16-NEXT: fadd v1.4s, v2.4s, v3.4s
@@ -263,7 +261,6 @@ define <7 x half> @fadd_v7f16(<7 x half> %a, <7 x half> %b) {
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v2.h[0]
; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[7], v0.h[0]
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: fadd_v7f16:
@@ -768,26 +765,24 @@ define <7 x half> @fsub_v7f16(<7 x half> %a, <7 x half> %b) {
;
; CHECK-GI-NOFP16-LABEL: fsub_v7f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[5]
-; CHECK-GI-NOFP16-NEXT: mov h4, v1.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h5, v1.h[5]
-; CHECK-GI-NOFP16-NEXT: fcvtl v6.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl v7.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[6]
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v1.4h
+; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[5]
+; CHECK-GI-NOFP16-NEXT: mov h6, v1.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h7, v1.h[5]
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v2.h[1], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: fsub v2.4s, v2.4s, v3.4s
+; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[6]
; CHECK-GI-NOFP16-NEXT: mov v4.h[1], v5.h[0]
-; CHECK-GI-NOFP16-NEXT: fsub v3.4s, v6.4s, v7.4s
-; CHECK-GI-NOFP16-NEXT: mov v2.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v4.h[2], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v3.4s
-; CHECK-GI-NOFP16-NEXT: mov v2.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v4.h[3], v0.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v6.h[1], v7.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v2.4s
+; CHECK-GI-NOFP16-NEXT: mov v4.h[2], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v6.h[2], v1.h[0]
; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[3]
-; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v2.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v4.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v4.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v6.4h
; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
; CHECK-GI-NOFP16-NEXT: fsub v1.4s, v2.4s, v3.4s
@@ -799,7 +794,6 @@ define <7 x half> @fsub_v7f16(<7 x half> %a, <7 x half> %b) {
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v2.h[0]
; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[7], v0.h[0]
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: fsub_v7f16:
diff --git a/llvm/test/CodeGen/AArch64/fcmp.ll b/llvm/test/CodeGen/AArch64/fcmp.ll
index 0f02784aaf32a0..2d0b5574cdd7ba 100644
--- a/llvm/test/CodeGen/AArch64/fcmp.ll
+++ b/llvm/test/Co...
[truncated]
|
madhur13490
reviewed
Mar 8, 2024
davemgreen
reviewed
Mar 11, 2024
| PrevMI->getOperand(0).setReg(I.getOperand(0).getReg()); | ||
| constrainSelectedInstRegOperands(*PrevMI, TII, TRI, RBI); | ||
| } else { |
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Could it set PrevMI = ScalarToVec above as a base-case instead? Or maybe always insert the COPY, either way is probably fine.
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I did try that at first, however that was giving a crash:
LLVM ERROR: VReg has no regclass after selection: %bv:fpr(<4 x s32>) = INSERT_SUBREG %3:fpr128(tied-def 0), %val:gpr32all(s32), %subreg.ssub (in function: undef_elts_different_regbanks)
in llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir. I think it is best to try and elide the copy wherever possible.
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I see. Which one? Setting PrevMI = ScalarToVec? It sound like the output of the variable could not be constrained as INSERT_SUBREG is a generic operation, would it work better if it was constrained to fpr128?
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The issue is coming from https://github.com/llvm/llvm-project/blob/main/llvm/lib/CodeGen/TargetInstrInfo.cpp#L58-L60. Like you said, it is because INSERT_SUBREG is a generic operation and it does work by constraining the register, so I have updated the patch to reflect that.
…ing G_BUILD_VECTOR It is safe to ignore undef values when selecting G_BUILD_VECTOR as undef values choose random registers for copying values from.
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aemerson
approved these changes
Mar 11, 2024
| DstVec = PrevMI->getOperand(0).getReg(); | ||
| Register OpReg = I.getOperand(i).getReg(); | ||
| // Do not emit inserts for undefs | ||
| if (!getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, OpReg, MRI)) { |
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You can do the shorter !getOpcodeDef<GImplicitDef>(OpReg, MRI)
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Sorry I mistyped, I've updated the previous comment with the right function name.
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Okay, I have updated the patch to use this call.
|
LGTM |
madhur13490
approved these changes
Mar 12, 2024
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It is safe to ignore undef values when selecting G_BUILD_VECTOR as undef values choose random registers for copying values from.