[X86] Remove SlowDivide tuning from GRTTuning #84676
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The DIV32/64 throughput was improved since Goldmont in the Atom architecture. The Alder Lake-E shows similar number too. So we shouldn't add such tunings to Gracemont and later architectures.
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@llvm/pr-subscribers-backend-x86 Author: Phoebe Wang (phoebewang) ChangesThe DIV32/64 throughput was improved since Goldmont in the Atom architecture. The Alder Lake-E shows similar number too. So we shouldn't add such tunings to Gracemont and later products. Checked from Agner Fog's table and uops.info. Full diff: https://github.com/llvm/llvm-project/pull/84676.diff 1 Files Affected:
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index a2a65ce75d6b9a..8367f938c0ddfa 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -1237,8 +1237,6 @@ def ProcessorFeatures {
// Gracemont
list<SubtargetFeature> GRTTuning = [TuningMacroFusion,
TuningSlow3OpsLEA,
- TuningSlowDivide32,
- TuningSlowDivide64,
TuningFastScalarFSQRT,
TuningFastVectorFSQRT,
TuningFast15ByteNOP,
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| @@ -1237,8 +1237,6 @@ def ProcessorFeatures { | |||
| // Gracemont | |||
| list<SubtargetFeature> GRTTuning = [TuningMacroFusion, | |||
| TuningSlow3OpsLEA, | |||
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LEA also seems to be reasonably fast on GRT.
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No sure. We have TuningSlow3OpsLEA for AlderLake and uops.info shows it has longer latency on it.
I don't have any information about newer targets.
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2c latency, but other slow lea is 3c. Bit of a middle ground.
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Interestingly, the latency was reduced to 1 since IceLake but was grown back to 2 on AlderLake.
I think we can change it for IceLake, but AlderLake etc. need more date provements.
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LGTM |
Done. |
The DIV32/64 throughput was improved since Goldmont in the Atom architecture. The Alder Lake-E shows similar number too. So we shouldn't add such tunings to Gracemont and later products.
Checked from Agner Fog's table and uops.info.