[RISCV] Add subtarget features for profiles #84877

wangpc-pp · 2024-03-12T06:28:20Z

This may simplify the usage of tools like opt, llc, etc.

Created using spr 1.3.4

llvmbot · 2024-03-12T06:28:50Z

@llvm/pr-subscribers-backend-risc-v
@llvm/pr-subscribers-clang

@llvm/pr-subscribers-clang-driver

Author: Wang Pengcheng (wangpc-pp)

Changes

As discussed in #76357 (comment),
we may need to add generic CPUs for profiles.

I don't know if we need S-mode profile CPUs.

Patch is 33.35 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/84877.diff

3 Files Affected:

(modified) clang/test/Driver/riscv-cpus.c (+319)
(modified) clang/test/Misc/target-invalid-cpu-note.c (+4-4)
(modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+216-8)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ff2bd6f7c8ba34..a285f0f9c41f54 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -302,3 +302,322 @@
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 -march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
 // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64
+
+// Check profile CPUs
+
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=generic-rvi20u32 | FileCheck -check-prefix=MCPU-GENERIC-RVI20U32 %s
+// MCPU-GENERIC-RVI20U32: "-target-cpu" "generic-rvi20u32"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-a"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-c"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-d"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-f"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-m"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-abi" "ilp32"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvi20u64 | FileCheck -check-prefix=MCPU-GENERIC-RVI20U64 %s
+// MCPU-GENERIC-RVI20U64: "-target-cpu" "generic-rvi20u64"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-a"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-c"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-d"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-f"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-m"
+// MCPU-GENERIC-RVI20U64-SAME: "-target-abi" "lp64"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20u64 | FileCheck -check-prefix=MCPU-GENERIC-RVA20U64 %s
+// MCPU-GENERIC-RVA20U64: "-target-cpu" "generic-rva20u64"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+m"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+a"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+f"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+d"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+c"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+za128rs"
+// MCPU-GENERIC-RVA20U64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20s64 | FileCheck -check-prefix=MCPU-GENERIC-RVA20S64 %s
+// MCPU-GENERIC-RVA20S64: "-target-cpu" "generic-rva20s64"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zifencei"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+za128rs"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ssccptr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvala"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvecd"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svade"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svbare"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva22u64 | FileCheck -check-prefix=MCPU-GENERIC-RVA22U64 %s
+// MCPU-GENERIC-RVA22U64: "-target-cpu" "generic-rva22u64"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zic64b"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbom"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbop"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicboz"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zihintpause"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zihpm"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+za64rs"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zfhmin"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zba"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zbb"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zbs"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zkt"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva22s64 | FileCheck -check-prefix=MCPU-GENERIC-RVA22S64 %s
+// MCPU-GENERIC-RVA22S64: "-target-cpu" "generic-rva22s64"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zic64b"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zicbom"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zicbop"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zicboz"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zifencei"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zihintpause"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zihpm"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+za64rs"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zfhmin"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zba"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zbb"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zbs"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+zkt"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+ssccptr"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+sscounterenw"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+sstvala"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+sstvecd"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+svade"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+svbare"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+svinval"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-feature" "+svpbmt"
+// MCPU-GENERIC-RVA22S64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva23u64 -menable-experimental-extensions \
+// RUN:   | FileCheck -check-prefix=MCPU-GENERIC-RVA23U64 %s
+// MCPU-GENERIC-RVA23U64: "-target-cpu" "generic-rva23u64"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+v"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zic64b"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicbom"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicbop"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicboz"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicond"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zihintntl"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zihintpause"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zihpm"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+experimental-zimop"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+za64rs"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zawrs"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zfa"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zfhmin"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zcb"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+experimental-zcmop"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zba"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zbb"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zbs"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zkt"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zvbb"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zvfhmin"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-feature" "+zvkt"
+// MCPU-GENERIC-RVA23U64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva23s64 -menable-experimental-extensions \
+// RUN:   | FileCheck -check-prefix=MCPU-GENERIC-RVA23S64 %s
+// MCPU-GENERIC-RVA23S64: "-target-cpu" "generic-rva23s64"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+v"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+h"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zic64b"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicbom"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicbop"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicboz"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicond"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zifencei"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zihintntl"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zihintpause"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zihpm"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+experimental-zimop"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+za64rs"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zawrs"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zfa"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zfhmin"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zcb"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+experimental-zcmop"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zba"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zbb"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zbs"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zkt"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zvbb"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zvfhmin"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+zvkt"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+shcounterenw"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+shgatpa"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+shtvala"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+shvsatpa"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+shvstvala"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+shvstvecd"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+ssccptr"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+sscofpmf"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+sscounterenw"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+experimental-ssnpm"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+ssstateen"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+sstc"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+sstvala"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+sstvecd"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+ssu64xl"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+svade"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+svbare"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+svinval"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+svnapot"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-feature" "+svpbmt"
+// MCPU-GENERIC-RVA23S64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvb23u64 -menable-experimental-extensions \
+// RUN:   | FileCheck -check-prefix=MCPU-GENERIC-RVB23U64 %s
+// MCPU-GENERIC-RVB23U64: "-target-cpu" "generic-rvb23u64"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zic64b"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicbom"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicbop"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicboz"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicond"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zihintntl"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zihintpause"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zihpm"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+experimental-zimop"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+za64rs"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zawrs"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zfa"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zcb"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+experimental-zcmop"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zba"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zbb"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zbs"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-feature" "+zkt"
+// MCPU-GENERIC-RVB23U64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvb23s64 -menable-experimental-extensions \
+// RUN:   | FileCheck -check-prefix=MCPU-GENERIC-RVB23S64 %s
+// MCPU-GENERIC-RVB23S64: "-target-cpu" "generic-rvb23s64"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zic64b"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicbom"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicbop"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicboz"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicond"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zifencei"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zihintntl"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zihintpause"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zihpm"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+experimental-zimop"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+za64rs"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zawrs"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zfa"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zcb"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+experimental-zcmop"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zba"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zbb"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zbs"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+zkt"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+ssccptr"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+sscofpmf"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+sscounterenw"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+sstc"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+sstvala"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+sstvecd"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+ssu64xl"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+svade"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+svbare"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+svinval"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+svnapot"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-feature" "+svpbmt"
+// MCPU-GENERIC-RVB23S64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=generic-rvm23u32 -menable-experimental-extensions \
+// RUN:   | FileCheck -check-prefix=MCPU-GENERIC-RVM23U32 %s
+// MCPU-GENERIC-RVM23U32: "-target-cpu" "generic-rvm23u32"
+// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zicbop"
+// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zicond"
+// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zihintntl"
+// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zihintpause"
+// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+experimental-zimop"
+// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zce"
+// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+experimental-zcmop"
+// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zba"
+// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zbb"
+// MCPU-GENERIC-RVM23U32-SAME: "-target-feature" "+zbs"
+// MCPU-GENERIC-RVM23U32-SAME: "-target-abi" "ilp32"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c
index b65a8fb057ee53..41347f9ed7aa14 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -81,16 +81,16 @@
 
 // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32
 // RISCV32: error: unknown target CPU 'not-a-cpu'
-// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max{{$}}
+// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, generic-rvi20u32, generic-rvm23u32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max{{$}}
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, gene...
[truncated]

michaelmaitland

LGTM

topperc · 2024-03-12T22:23:46Z

I don't know if we need S-mode profile CPUs.

I lean towards not supporting them since the S extensions don't do anything in the compiler except preprocessor defines and ELF attributes, but maybe we should put it on the agenda for the sync meeting this week.

asb · 2024-03-14T15:01:31Z

I don't know if we need S-mode profile CPUs.

I lean towards not supporting them since the S extensions don't do anything in the compiler except preprocessor defines and ELF attributes, but maybe we should put it on the agenda for the sync meeting this week.

My initial feeling is it probably wouldn't hurt to have them, but it's not clear who would use them in practice. Build systems for userspace code presumably wouldn't do so, and I'd have thought kernels would typically want more control (as they wouldn't want the compiler to make use of floating point or vectors freely). But I could be wrong on that, so I'd love to hear from others with more experience on that. e.g. @petrhosek

asb · 2024-03-14T16:56:15Z

We discussed this on the sync-up call and @preames very rightly pointed out that we should take a step back here...from a user perspective, what does specifying a profile via -mcpu provide that specifying it via -march doesn't? We weren't able to answer that in the call, but perhaps we're missing something?

wangpc-pp · 2024-03-14T18:15:10Z

We discussed this on the sync-up call and @preames very rightly pointed out that we should take a step back here...from a user perspective, what does specifying a profile via -mcpu provide that specifying it via -march doesn't? We weren't able to answer that in the call, but perhaps we're missing something?

Thanks! I was off the meeting because of some real-life issues. :-)

The story is:

I was implementing the profile name in -march, and I exposed profiles as subtarget features at the first time. So that we can use -mattr=+<profile name> and simplify the definitions of processors. You may see the context in [RISCV] Support RISC-V Profiles in -march option #76357 (comment).
@topperc suggested that we may not need these features and we can refactor out some feature lists and may add -mcpu=generic-<profile>. I like this idea and so I created this PR.

As for the difference, we can specify -mcpu for llc and other tools, which is not the case for -march? I hope we can simplify the commands when we try to do some tests. (Though this is an use for compiler developers, not for real users).

Created using spr 1.3.4

github-actions · 2024-03-25T03:46:36Z

✅ With the latest revision this PR passed the C/C++ code formatter.

github-actions · 2024-03-25T03:46:36Z

✅ With the latest revision this PR passed the Python code formatter.

Created using spr 1.3.6-beta.1

wangpc-pp · 2024-04-17T05:27:20Z

Ping.

wangpc-pp · 2024-04-25T05:31:24Z

Gentle ping.

asb · 2024-04-25T16:38:57Z

We discussed again in the sync-up call to try to move this forwards and per a discussion with @topperc and @preames were wondering if relying on -mattr and a corresponding feature for the profile might be the better approach after all.

There's not a lot of instances of this, but I do see at least some ARM tests using -mattr=+armv8.2-a or +armv8.3-a. So there's some precedent there.
- Looking again, x86 does indeed use -mcpu in llc for x86_64-v3 etc. So that could be an argument for following suit, but for some reason it still feels like defining new generic CPUs isn't very consistent with how we normally specific extensions in RISC-V. So -march for clang and -mattr for llc feels consistent to me.
Philip raised the point that if we're making this change primarily to ease usage of llc, it's unfortunate if we're adding something that is exposed to clang that we wouldn't necessarily want otherwise (in this case, the generic cpu for the profile).

That said, it was a brief discussion and we may have missed something or Philip or Craig may have more thoughts afterwards.

Do you see any disadvantage to going back to adding a feature for the profiles?

wangpc-pp · 2024-04-25T17:02:24Z

Do you see any disadvantage to going back to adding a feature for the profiles?

Of course not, I will revise this patch tomorrow. Thanks for discussing this!
(I missed the sync-up meeting because I forgot the daylight saving...)

Created using spr 1.3.6-beta.1

llvm/lib/Target/RISCV/RISCVSubtarget.h

Created using spr 1.3.6-beta.1

Created using spr 1.3.6-beta.1 [skip ci]

Created using spr 1.3.6-beta.1

wangpc-pp · 2024-04-28T03:34:02Z

I don't know why spr added so many reviewers... sorry for bothering.

[𝘀𝗽𝗿] initial version

ec68548

Created using spr 1.3.4

llvmbot added clang Clang issues not falling into any other category backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' labels Mar 12, 2024

wangpc-pp requested review from asb, preames, kito-cheng, michaelmaitland and topperc March 12, 2024 06:29

michaelmaitland approved these changes Mar 12, 2024

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Remove genenic prefix

dc37018

Created using spr 1.3.4

dinyy mentioned this pull request Apr 16, 2024

Is there any generic cpu model support for RVV？Or how to add a cpu model for RISCV? #88851

Open

Rebase

452cbe8

Created using spr 1.3.6-beta.1

Expose features instead of CPUs

3ffb796

Created using spr 1.3.6-beta.1

wangpc-pp changed the title ~~[RISCV] Add generic CPUs for profiles~~ [RISCV] Add subtarget features for profiles Apr 26, 2024

kito-cheng reviewed Apr 26, 2024

View reviewed changes

llvm/lib/Target/RISCV/RISCVSubtarget.h Outdated Show resolved Hide resolved

wangpc-pp added 3 commits April 26, 2024 15:59

We should add FeatureStdExtI explicitly now

e03f2cd

Created using spr 1.3.6-beta.1

[𝘀𝗽𝗿] changes introduced through rebase

c5f08b6

Created using spr 1.3.6-beta.1 [skip ci]

Rebase

0fdb150

Created using spr 1.3.6-beta.1

wangpc-pp requested review from matthias-springer, dcaballe, hanhanW, JDevlieghere, tbaederr, Endilll, nikic and a team as code owners April 28, 2024 03:32

wangpc-pp changed the base branch from users/wangpc-pp/spr/main.riscv-add-subtarget-features-for-profiles to main April 28, 2024 03:32

wangpc-pp merged commit f86d264 into main Apr 28, 2024
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wangpc-pp deleted the users/wangpc-pp/spr/riscv-add-generic-cpus-for-profiles branch April 28, 2024 03:32

wangpc-pp removed request for a team, nikic, rupprecht, JDevlieghere, aaupov, matthias-springer, dcci, hanhanW, maksfb, rafaelauler, Endilll, dcaballe, PeimingLiu, aartbik, ayermolo, tbaederr and yinying-lisa-li April 28, 2024 03:35

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[RISCV] Add subtarget features for profiles #84877

[RISCV] Add subtarget features for profiles #84877

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[RISCV] Add subtarget features for profiles #84877

[RISCV] Add subtarget features for profiles #84877

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