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[SelectionDAG] Add MaskedValueIsZero check to allow folding of zero extended variables we know are safe to extend #85573

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merged 2 commits into from
Mar 21, 2024

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@AtariDreams AtariDreams commented Mar 17, 2024

Add ones for every high bit that will cleared.

This will allow us to evaluate variables that have their bits known to see if they have no risk of overflow despite the shift amount being greater than the difference between the two types.

@llvmbot llvmbot added the llvm:SelectionDAG SelectionDAGISel as well label Mar 17, 2024
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llvmbot commented Mar 17, 2024

@llvm/pr-subscribers-backend-x86

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Author: AtariDreams (AtariDreams)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/85573.diff

1 Files Affected:

  • (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+11-3)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index b6a5925123f13f..e733916eaeefdb 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -13802,11 +13802,19 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
         if (N0.getOpcode() == ISD::SHL) {
           // If the original shl may be shifting out bits, do not perform this
           // transformation.
-          // TODO: Add MaskedValueIsZero check.
           unsigned KnownZeroBits = ShVal.getValueSizeInBits() -
                                    ShVal.getOperand(0).getValueSizeInBits();
-          if (ShAmtC->getAPIntValue().ugt(KnownZeroBits))
-            return SDValue();
+          if (ShAmtC->getAPIntValue().ugt(KnownZeroBits)) {
+            // Create a mask that has ones for the bits being shifted out.
+            llvm::APInt ShiftOutMask = llvm::APInt::getHighBitsSet(
+                ShVal.getValueSizeInBits(),
+                ShAmtC->getAPIntValue().getZExtValue());
+
+            // Check if the bits being shifted out are known to be zero.
+            if (!DAG.MaskedValueIsZero(ShVal, ShiftOutMask)) {
+              return SDValue();
+            }
+          }
         }
 
         // Ensure that the shift amount is wide enough for the shifted value.

@AtariDreams AtariDreams changed the title Add MaskedValueIsZero check [SelectionDAG] Replace KnownZeros ugt check with MaskedValueIsZero check Mar 17, 2024
@AtariDreams AtariDreams changed the title [SelectionDAG] Replace KnownZeros ugt check with MaskedValueIsZero check [SelectionDAG] Add MaskedValueIsZero check to allow folding of zero extended variables we know are safe to extend Mar 18, 2024
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Outdated Show resolved Hide resolved
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@arsenm @RKSimon addressed!

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github-actions bot commented Mar 19, 2024

✅ With the latest revision this PR passed the C/C++ code formatter.

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arsenm commented Mar 20, 2024

clang-format error

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clang-format error

@arsenm Fixed!

…xtended variables we know are safe to extend

Add ones for every high bit that will cleared.

This will allow us to evaluate variables that have their bits known to see if they have no risk of overflow despite the shift amount being greater than the difference between the two types.
@arsenm arsenm merged commit 7e72caf into llvm:main Mar 21, 2024
4 checks passed
@AtariDreams AtariDreams deleted the NX branch March 21, 2024 14:04
chencha3 pushed a commit to chencha3/llvm-project that referenced this pull request Mar 23, 2024
…xtended variables we know are safe to extend (llvm#85573)

Add ones for every high bit that will cleared.

This will allow us to evaluate variables that have their bits known to
see if they have no risk of overflow despite the shift amount being
greater than the difference between the two types.
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4 participants