[CodeGen] Add default lowering for llvm.allow.{runtime,ubsan}.check() #86049
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Created using spr 1.3.4 [skip ci]
Created using spr 1.3.4
llvmbot
added
backend:AArch64
backend:AMDGPU
backend:X86
llvm:globalisel
llvm:SelectionDAG
|
@llvm/pr-subscribers-backend-x86 @llvm/pr-subscribers-llvm-selectiondag Author: Vitaly Buka (vitalybuka) ChangesRFC: https://discourse.llvm.org/t/rfc-add-llvm-experimental-hot-intrinsic-or-llvm-hot/77641 Full diff: https://github.com/llvm/llvm-project/pull/86049.diff 10 Files Affected:
diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp
index 9f99bb7e693f7e..e657872c382848 100644
--- a/llvm/lib/CodeGen/CodeGenPrepare.cpp
+++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp
@@ -2462,8 +2462,10 @@ bool CodeGenPrepare::optimizeCallInst(CallInst *CI, ModifyDT &ModifiedDT) {
break;
case Intrinsic::assume:
llvm_unreachable("llvm.assume should have been removed already");
+ case Intrinsic::allow_runtime_check:
+ case Intrinsic::allow_ubsan_check:
case Intrinsic::experimental_widenable_condition: {
- // Give up on future widening oppurtunties so that we can fold away dead
+ // Give up on future widening opportunities so that we can fold away dead
// paths and merge blocks before going into block-local instruction
// selection.
if (II->use_empty()) {
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 757af3b1c4fe82..0811c565386654 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -2475,6 +2475,11 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
Info.OrigRet = {Register(), Type::getVoidTy(CI.getContext()), 0};
return CLI->lowerCall(MIRBuilder, Info);
}
+ case Intrinsic::allow_runtime_check:
+ case Intrinsic::allow_ubsan_check:
+ MIRBuilder.buildCopy(getOrCreateVReg(CI),
+ getOrCreateVReg(*ConstantInt::getTrue(CI.getType())));
+ return true;
case Intrinsic::amdgcn_cs_chain:
return translateCallBase(CI, MIRBuilder);
case Intrinsic::fptrunc_round: {
diff --git a/llvm/lib/CodeGen/IntrinsicLowering.cpp b/llvm/lib/CodeGen/IntrinsicLowering.cpp
index 09d282d12c5fb1..45fba4341ad007 100644
--- a/llvm/lib/CodeGen/IntrinsicLowering.cpp
+++ b/llvm/lib/CodeGen/IntrinsicLowering.cpp
@@ -243,6 +243,11 @@ void IntrinsicLowering::LowerIntrinsicCall(CallInst *CI) {
break;
}
+ case Intrinsic::allow_runtime_check:
+ case Intrinsic::allow_ubsan_check:
+ CI->replaceAllUsesWith(ConstantInt::getTrue(CI->getType()));
+ return;
+
case Intrinsic::ctpop:
CI->replaceAllUsesWith(LowerCTPOP(Context, CI->getArgOperand(0), CI));
break;
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
index 27b8472ddb73d8..ce5a7ea09d476f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -1452,6 +1452,10 @@ bool FastISel::selectIntrinsicCall(const IntrinsicInst *II) {
case Intrinsic::is_constant:
llvm_unreachable("llvm.is.constant.* should have been lowered already");
+ case Intrinsic::allow_runtime_check:
+ case Intrinsic::allow_ubsan_check:
+ llvm_unreachable("llvm.*.check should have been lowered already");
+
case Intrinsic::launder_invariant_group:
case Intrinsic::strip_invariant_group:
case Intrinsic::expect: {
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 2d63774c75e372..51c9af6d62d96b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -7322,6 +7322,11 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
return;
}
+ case Intrinsic::allow_runtime_check:
+ case Intrinsic::allow_ubsan_check:
+ setValue(&I, getValue(ConstantInt::getTrue(I.getType())));
+ return;
+
case Intrinsic::uadd_with_overflow:
case Intrinsic::sadd_with_overflow:
case Intrinsic::usub_with_overflow:
diff --git a/llvm/test/CodeGen/AArch64/allow-check.ll b/llvm/test/CodeGen/AArch64/allow-check.ll
new file mode 100644
index 00000000000000..c315b216e222c0
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/allow-check.ll
@@ -0,0 +1,30 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 -global-isel | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 -fast-isel | FileCheck %s
+
+target triple = "aarch64-linux"
+
+define i1 @test_runtime() local_unnamed_addr {
+; CHECK-LABEL: test_runtime:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w0, #1 // =0x1
+; CHECK-NEXT: ret
+entry:
+ %allow = call i1 @llvm.allow.runtime.check(metadata !"test_check")
+ ret i1 %allow
+}
+
+declare i1 @llvm.allow.runtime.check(metadata) nounwind
+
+define i1 @test_ubsan() local_unnamed_addr {
+; CHECK-LABEL: test_ubsan:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w0, #1 // =0x1
+; CHECK-NEXT: ret
+entry:
+ %allow = call i1 @llvm.allow.ubsan.check(i8 7)
+ ret i1 %allow
+}
+
+declare i1 @llvm.allow.ubsan.check(i8) nounwind
diff --git a/llvm/test/CodeGen/AMDGPU/allow-check.ll b/llvm/test/CodeGen/AMDGPU/allow-check.ll
new file mode 100644
index 00000000000000..db6cdc30493d88
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/allow-check.ll
@@ -0,0 +1,30 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d | FileCheck %s
+; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -global-isel | FileCheck %s
+; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -fast-isel | FileCheck %s
+
+define i1 @test_runtime() local_unnamed_addr {
+; CHECK-LABEL: test_runtime:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_mov_b32_e32 v0, 1
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %allow = call i1 @llvm.allow.runtime.check(metadata !"test_check")
+ ret i1 %allow
+}
+
+declare i1 @llvm.allow.runtime.check(metadata) nounwind
+
+define i1 @test_ubsan() local_unnamed_addr {
+; CHECK-LABEL: test_ubsan:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_mov_b32_e32 v0, 1
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %allow = call i1 @llvm.allow.ubsan.check(i8 7)
+ ret i1 %allow
+}
+
+declare i1 @llvm.allow.ubsan.check(i8) nounwind
diff --git a/llvm/test/CodeGen/Generic/allow-check.ll b/llvm/test/CodeGen/Generic/allow-check.ll
new file mode 100644
index 00000000000000..88412f552d1378
--- /dev/null
+++ b/llvm/test/CodeGen/Generic/allow-check.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -O3
+; RUN: llc < %s -O3 -global-isel
+; RUN: llc < %s -O3 -fast-isel
+
+; RUN: llc < %s -O0
+; RUN: llc < %s -O0 -global-isel
+; RUN: llc < %s -O0 -fast-isel
+
+define i1 @test_runtime() local_unnamed_addr {
+entry:
+ %allow = call i1 @llvm.allow.runtime.check(metadata !"test_check")
+ ret i1 %allow
+}
+
+declare i1 @llvm.allow.runtime.check(metadata) nounwind
+
+define i1 @test_ubsan() local_unnamed_addr {
+entry:
+ %allow = call i1 @llvm.allow.ubsan.check(i8 7)
+ ret i1 %allow
+}
+
+declare i1 @llvm.allow.ubsan.check(i8) nounwind
diff --git a/llvm/test/CodeGen/RISCV/allow-check.ll b/llvm/test/CodeGen/RISCV/allow-check.ll
new file mode 100644
index 00000000000000..2ac6370adbd5cf
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/allow-check.ll
@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=riscv32 | FileCheck %s
+; RUN: llc < %s -mtriple=riscv64 | FileCheck %s
+; RUN: llc < %s -mtriple=riscv32 -global-isel | FileCheck %s
+; RUN: llc < %s -mtriple=riscv64 -global-isel | FileCheck %s
+; RUN: llc < %s -mtriple=riscv32 -fast-isel=true | FileCheck %s
+; RUN: llc < %s -mtriple=riscv64 -fast-isel=true | FileCheck %s
+
+define i1 @test_runtime() local_unnamed_addr {
+; CHECK-LABEL: test_runtime:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li a0, 1
+; CHECK-NEXT: ret
+entry:
+ %allow = call i1 @llvm.allow.runtime.check(metadata !"test_check")
+ ret i1 %allow
+}
+
+declare i1 @llvm.allow.runtime.check(metadata) nounwind
+
+define i1 @test_ubsan() local_unnamed_addr {
+; CHECK-LABEL: test_ubsan:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li a0, 1
+; CHECK-NEXT: ret
+entry:
+ %allow = call i1 @llvm.allow.ubsan.check(i8 7)
+ ret i1 %allow
+}
+
+declare i1 @llvm.allow.ubsan.check(i8) nounwind
diff --git a/llvm/test/CodeGen/X86/allow-check.ll b/llvm/test/CodeGen/X86/allow-check.ll
new file mode 100644
index 00000000000000..3f0bb1837b22aa
--- /dev/null
+++ b/llvm/test/CodeGen/X86/allow-check.ll
@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=x86_64 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64 -global-isel | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64 -fast-isel | FileCheck %s
+
+define i1 @test_runtime() local_unnamed_addr {
+; CHECK-LABEL: test_runtime:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movb $1, %al
+; CHECK-NEXT: retq
+entry:
+ %allow = call i1 @llvm.allow.runtime.check(metadata !"test_check")
+ ret i1 %allow
+}
+
+declare i1 @llvm.allow.runtime.check(metadata) nounwind
+
+define i1 @test_ubsan() local_unnamed_addr {
+; CHECK-LABEL: test_ubsan:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movb $1, %al
+; CHECK-NEXT: retq
+entry:
+ %allow = call i1 @llvm.allow.ubsan.check(i8 7)
+ ret i1 %allow
+}
+
+declare i1 @llvm.allow.ubsan.check(i8) nounwind
|
Created using spr 1.3.4 [skip ci]
arsenm
reviewed
Mar 21, 2024
Created using spr 1.3.4 [skip ci]
Created using spr 1.3.4
Created using spr 1.3.4
arsenm
approved these changes
Mar 22, 2024
Created using spr 1.3.4 [skip ci]
vitalybuka
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users/vitalybuka/spr/main.codegen-add-default-lowering-for-llvmallowruntimeubsancheck
to
main
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Follow up to #86049. clang-armv8-quick build bot can trigger this branch.
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RFC: https://discourse.llvm.org/t/rfc-add-llvm-experimental-hot-intrinsic-or-llvm-hot/77641