[SelectionDAG] Use computeForAddSub to prove that ISD::ADD is not 0

[AtariDreams]

No description provided.

[llvmbot]

@llvm/pr-subscribers-llvm-selectiondag

Author: AtariDreams (AtariDreams)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/86453.diff

1 Files Affected:

• (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (+8-1)

diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 0ab5142ab81676..8e79ab9541676b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5405,7 +5405,14 @@ bool SelectionDAG::isKnownNeverZero(SDValue Op, unsigned Depth) const {
       if (isKnownNeverZero(Op.getOperand(1), Depth + 1) ||
           isKnownNeverZero(Op.getOperand(0), Depth + 1))
         return true;
-    // TODO: There are a lot more cases we can prove for add.
+    if (KnownBits::computeForAddSub(
+            true, Op->getFlags().hasNoSignedWrap(),
+            Op->getFlags().hasNoUnsignedWrap(),
+            computeKnownBits(Op.getOperand(0), Depth + 1),
+            computeKnownBits(Op.getOperand(1), Depth + 1))
+            .isNonZero())
+      return true;
+    // TODO: Are there more cases we can prove for add not covered by the above?
     break;
 
   case ISD::SUB: {

[github-actions]

✅ With the latest revision this PR passed the C/C++ code formatter.

[github-actions]

✅ With the latest revision this PR passed the Python code formatter.

[topperc]

Don't we call computeKnownBits(Op, Depth).isNonZero(); after the switch in this function? That does the same thing as this in a more general way.

[RKSimon]

@AtariDreams Its great that you're working through the (far too many.......) TODOs in the codebase, but you have to begin with creating tests that show the missing functionality, not just add code and hope it gets tested.