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[AMDGPU][NFC] Rename Feature GFX11FullVGPRs to 1_5xVGPRs #86468
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mariusz-sikora-at-amd
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mariusz-sikora-at-amd:masikora/pub-nfc-rename-full-vgpr
Mar 25, 2024
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[AMDGPU][NFC] Rename Feature GFX11FullVGPRs to 1_5xVGPRs #86468
mariusz-sikora-at-amd
merged 1 commit into
llvm:main
from
mariusz-sikora-at-amd:masikora/pub-nfc-rename-full-vgpr
Mar 25, 2024
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@llvm/pr-subscribers-backend-amdgpu Author: Mariusz Sikora (mariusz-sikora-at-amd) ChangesFull diff: https://github.com/llvm/llvm-project/pull/86468.diff 3 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index c877658cd38e2b..37dcfef3b2a3da 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -831,10 +831,12 @@ def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard",
"Does not need SW waitstates"
>;
-def FeatureGFX11FullVGPRs : SubtargetFeature<"gfx11-full-vgprs",
- "HasGFX11FullVGPRs",
+// Allocate 1536 VGPRs for wave32 and 768 VGPRs for wave64
+// with allocation granularity 24 for wave32 and 12 for wave64
+def Feature1_5xVGPRs : SubtargetFeature<"allocate1_5xvgprs",
+ "Has1_5xVGPRs",
"true",
- "GFX11 with 50% more physical VGPRs and 50% larger allocation granule than GFX10"
+ "Has 50% more physical VGPRs and 50% larger allocation granule"
>;
@@ -1491,12 +1493,12 @@ def FeatureISAVersion11_0_Common : FeatureSet<
def FeatureISAVersion11_0_0 : FeatureSet<
!listconcat(FeatureISAVersion11_0_Common.Features,
- [FeatureGFX11FullVGPRs,
+ [Feature1_5xVGPRs,
FeatureUserSGPRInit16Bug])>;
def FeatureISAVersion11_0_1 : FeatureSet<
!listconcat(FeatureISAVersion11_0_Common.Features,
- [FeatureGFX11FullVGPRs])>;
+ [Feature1_5xVGPRs])>;
def FeatureISAVersion11_0_2 : FeatureSet<
!listconcat(FeatureISAVersion11_0_Common.Features,
@@ -1517,7 +1519,7 @@ def FeatureISAVersion11_5_1 : FeatureSet<
[FeatureSALUFloatInsts,
FeatureDPPSrc1SGPR,
FeatureVGPRSingleUseHintInsts,
- FeatureGFX11FullVGPRs])>;
+ Feature1_5xVGPRs])>;
def FeatureISAVersion12 : FeatureSet<
[FeatureGFX12,
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index ca51da659c3311..4da10beabe3162 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -223,7 +223,7 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
bool HasImageStoreD16Bug = false;
bool HasImageGather4D16Bug = false;
bool HasMSAALoadDstSelBug = false;
- bool HasGFX11FullVGPRs = false;
+ bool Has1_5xVGPRs = false;
bool HasMADIntraFwdBug = false;
bool HasVOPDInsts = false;
bool HasVALUTransUseHazard = false;
@@ -1202,7 +1202,7 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
/// target.
bool hasNullExportTarget() const { return !GFX11Insts; }
- bool hasGFX11FullVGPRs() const { return HasGFX11FullVGPRs; }
+ bool has1_5xVGPRs() const { return Has1_5xVGPRs; }
bool hasVOPDInsts() const { return HasVOPDInsts; }
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 6d53f68ace70df..617681376a1bec 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -1081,7 +1081,7 @@ unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
*EnableWavefrontSize32 :
STI->getFeatureBits().test(FeatureWavefrontSize32);
- if (STI->getFeatureBits().test(FeatureGFX11FullVGPRs))
+ if (STI->getFeatureBits().test(Feature1_5xVGPRs))
return IsWave32 ? 24 : 12;
if (hasGFX10_3Insts(*STI))
@@ -1108,7 +1108,7 @@ unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI) {
if (!isGFX10Plus(*STI))
return 256;
bool IsWave32 = STI->getFeatureBits().test(FeatureWavefrontSize32);
- if (STI->getFeatureBits().test(FeatureGFX11FullVGPRs))
+ if (STI->getFeatureBits().test(Feature1_5xVGPRs))
return IsWave32 ? 1536 : 768;
return IsWave32 ? 1024 : 512;
}
|
✅ With the latest revision this PR passed the C/C++ code formatter. |
✅ With the latest revision this PR passed the Python code formatter. |
arsenm
approved these changes
Mar 25, 2024
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