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[AMDGPU] Add type-generic llvm.amdgcn.readfirstlane2 intrinsic #87334

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@jayfoad jayfoad commented Apr 2, 2024

  • [AMDGPU] Generate readfirstlane checks
  • [AMDGPU] Add type-generic llvm.amdgcn.readfirstlane2 intrinsic

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jayfoad commented Apr 2, 2024

Prior art:
https://reviews.llvm.org/D84639
https://reviews.llvm.org/D86154
https://reviews.llvm.org/D147732

TODO:

  • GlobalISel
  • readlane, writelane, others?

This patch tries to legalize readfirstlane2 for all legal types, but it should probably work on illegal types like i999 too. Is there a way to implement that for a target intrinsic in SelectionDAG? The only way I could see was with a pre-legalization combine, but I am not sure if it is OK to rely on a combine for legalization.

@@ -2206,11 +2206,18 @@ class AMDGPUWaveReduce<LLVMType data_ty = llvm_anyint_ty> : Intrinsic<
def int_amdgcn_wave_reduce_umin : AMDGPUWaveReduce;
def int_amdgcn_wave_reduce_umax : AMDGPUWaveReduce;

// i32 llvm.amdgcn.readfirstlane(i32)
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I think we should just upgrade the intrinsic instead of introducing a new copy

@@ -1,71 +1,176 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope %s
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global-isel checks

%x = call float @llvm.amdgcn.readfirstlane2.f32(float %src)
call void asm sideeffect "; use $0", "s"(float %x)
ret void
}
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Check bfloat, vector bfloat/half, float2, some pointers/pointer vectors

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What is float2? Done the others.

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<2 x float>

MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits());
return DAG.getBitcast(
VT, DAG.getAnyExtOrTrunc(
DAG.getNode(AMDGPUISD::READFIRSTLANE, DL, MVT::i32,
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Maybe directly accept legal 32-bit types and avoid the bitcast?

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