[MachineCombiner][NFC] Split target-dependent patterns #87991
Merged
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Created using spr 1.3.6-beta.1
|
@llvm/pr-subscribers-backend-x86 @llvm/pr-subscribers-backend-powerpc Author: Pengcheng Wang (wangpc-pp) ChangesWe split target-dependent MachineCombiner patterns to their target This makes MachineCombiner much more target-independent. Patch is 108.59 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/87991.diff 12 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/MachineCombinerPattern.h b/llvm/include/llvm/CodeGen/MachineCombinerPattern.h
index 89eed7463bd783..ed87667662663a 100644
--- a/llvm/include/llvm/CodeGen/MachineCombinerPattern.h
+++ b/llvm/include/llvm/CodeGen/MachineCombinerPattern.h
@@ -16,8 +16,16 @@
namespace llvm {
+/// The combiner's goal may differ based on which pattern it is attempting
+/// to optimize.
+enum class CombinerObjective {
+ MustReduceDepth, // The data dependency chain must be improved.
+ MustReduceRegisterPressure, // The register pressure must be reduced.
+ Default // The critical path must not be lengthened.
+};
+
/// These are instruction patterns matched by the machine combiner pass.
-enum class MachineCombinerPattern {
+enum MachineCombinerPattern {
// These are commutative variants for reassociating a computation chain. See
// the comments before getMachineCombinerPatterns() in TargetInstrInfo.cpp.
REASSOC_AX_BY,
@@ -25,161 +33,7 @@ enum class MachineCombinerPattern {
REASSOC_XA_BY,
REASSOC_XA_YB,
- // These are patterns matched by the PowerPC to reassociate FMA chains.
- REASSOC_XY_AMM_BMM,
- REASSOC_XMM_AMM_BMM,
-
- // These are patterns matched by the PowerPC to reassociate FMA and FSUB to
- // reduce register pressure.
- REASSOC_XY_BCA,
- REASSOC_XY_BAC,
-
- // These are patterns used to reduce the length of dependence chain.
- SUBADD_OP1,
- SUBADD_OP2,
-
- // These are multiply-add patterns matched by the AArch64 machine combiner.
- MULADDW_OP1,
- MULADDW_OP2,
- MULSUBW_OP1,
- MULSUBW_OP2,
- MULADDWI_OP1,
- MULSUBWI_OP1,
- MULADDX_OP1,
- MULADDX_OP2,
- MULSUBX_OP1,
- MULSUBX_OP2,
- MULADDXI_OP1,
- MULSUBXI_OP1,
- // NEON integers vectors
- MULADDv8i8_OP1,
- MULADDv8i8_OP2,
- MULADDv16i8_OP1,
- MULADDv16i8_OP2,
- MULADDv4i16_OP1,
- MULADDv4i16_OP2,
- MULADDv8i16_OP1,
- MULADDv8i16_OP2,
- MULADDv2i32_OP1,
- MULADDv2i32_OP2,
- MULADDv4i32_OP1,
- MULADDv4i32_OP2,
-
- MULSUBv8i8_OP1,
- MULSUBv8i8_OP2,
- MULSUBv16i8_OP1,
- MULSUBv16i8_OP2,
- MULSUBv4i16_OP1,
- MULSUBv4i16_OP2,
- MULSUBv8i16_OP1,
- MULSUBv8i16_OP2,
- MULSUBv2i32_OP1,
- MULSUBv2i32_OP2,
- MULSUBv4i32_OP1,
- MULSUBv4i32_OP2,
-
- MULADDv4i16_indexed_OP1,
- MULADDv4i16_indexed_OP2,
- MULADDv8i16_indexed_OP1,
- MULADDv8i16_indexed_OP2,
- MULADDv2i32_indexed_OP1,
- MULADDv2i32_indexed_OP2,
- MULADDv4i32_indexed_OP1,
- MULADDv4i32_indexed_OP2,
-
- MULSUBv4i16_indexed_OP1,
- MULSUBv4i16_indexed_OP2,
- MULSUBv8i16_indexed_OP1,
- MULSUBv8i16_indexed_OP2,
- MULSUBv2i32_indexed_OP1,
- MULSUBv2i32_indexed_OP2,
- MULSUBv4i32_indexed_OP1,
- MULSUBv4i32_indexed_OP2,
-
- // Floating Point
- FMULADDH_OP1,
- FMULADDH_OP2,
- FMULSUBH_OP1,
- FMULSUBH_OP2,
- FMULADDS_OP1,
- FMULADDS_OP2,
- FMULSUBS_OP1,
- FMULSUBS_OP2,
- FMULADDD_OP1,
- FMULADDD_OP2,
- FMULSUBD_OP1,
- FMULSUBD_OP2,
- FNMULSUBH_OP1,
- FNMULSUBS_OP1,
- FNMULSUBD_OP1,
- FMLAv1i32_indexed_OP1,
- FMLAv1i32_indexed_OP2,
- FMLAv1i64_indexed_OP1,
- FMLAv1i64_indexed_OP2,
- FMLAv4f16_OP1,
- FMLAv4f16_OP2,
- FMLAv8f16_OP1,
- FMLAv8f16_OP2,
- FMLAv2f32_OP2,
- FMLAv2f32_OP1,
- FMLAv2f64_OP1,
- FMLAv2f64_OP2,
- FMLAv4i16_indexed_OP1,
- FMLAv4i16_indexed_OP2,
- FMLAv8i16_indexed_OP1,
- FMLAv8i16_indexed_OP2,
- FMLAv2i32_indexed_OP1,
- FMLAv2i32_indexed_OP2,
- FMLAv2i64_indexed_OP1,
- FMLAv2i64_indexed_OP2,
- FMLAv4f32_OP1,
- FMLAv4f32_OP2,
- FMLAv4i32_indexed_OP1,
- FMLAv4i32_indexed_OP2,
- FMLSv1i32_indexed_OP2,
- FMLSv1i64_indexed_OP2,
- FMLSv4f16_OP1,
- FMLSv4f16_OP2,
- FMLSv8f16_OP1,
- FMLSv8f16_OP2,
- FMLSv2f32_OP1,
- FMLSv2f32_OP2,
- FMLSv2f64_OP1,
- FMLSv2f64_OP2,
- FMLSv4i16_indexed_OP1,
- FMLSv4i16_indexed_OP2,
- FMLSv8i16_indexed_OP1,
- FMLSv8i16_indexed_OP2,
- FMLSv2i32_indexed_OP1,
- FMLSv2i32_indexed_OP2,
- FMLSv2i64_indexed_OP1,
- FMLSv2i64_indexed_OP2,
- FMLSv4f32_OP1,
- FMLSv4f32_OP2,
- FMLSv4i32_indexed_OP1,
- FMLSv4i32_indexed_OP2,
-
- FMULv2i32_indexed_OP1,
- FMULv2i32_indexed_OP2,
- FMULv2i64_indexed_OP1,
- FMULv2i64_indexed_OP2,
- FMULv4i16_indexed_OP1,
- FMULv4i16_indexed_OP2,
- FMULv4i32_indexed_OP1,
- FMULv4i32_indexed_OP2,
- FMULv8i16_indexed_OP1,
- FMULv8i16_indexed_OP2,
-
- // RISCV FMADD, FMSUB, FNMSUB patterns
- FMADD_AX,
- FMADD_XA,
- FMSUB,
- FNMSUB,
-
- // X86 VNNI
- DPWSSD,
-
- FNMADD,
+ TARGET_PATTERN_START
};
} // end namespace llvm
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 9fd0ebe6956fbe..658092e192dd33 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -19,6 +19,7 @@
#include "llvm/ADT/Uniformity.h"
#include "llvm/CodeGen/MIRFormatter.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineCombinerPattern.h"
#include "llvm/CodeGen/MachineCycleAnalysis.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
@@ -61,7 +62,6 @@ class TargetRegisterClass;
class TargetRegisterInfo;
class TargetSchedModel;
class TargetSubtargetInfo;
-enum class MachineCombinerPattern;
enum class MachineTraceStrategy;
template <class T> class SmallVectorImpl;
@@ -1191,10 +1191,9 @@ class TargetInstrInfo : public MCInstrInfo {
/// faster sequence.
/// \param Root - Instruction that could be combined with one of its operands
/// \param Patterns - Vector of possible combination patterns
- virtual bool
- getMachineCombinerPatterns(MachineInstr &Root,
- SmallVectorImpl<MachineCombinerPattern> &Patterns,
- bool DoRegPressureReduce) const;
+ virtual bool getMachineCombinerPatterns(MachineInstr &Root,
+ SmallVectorImpl<int> &Patterns,
+ bool DoRegPressureReduce) const;
/// Return true if target supports reassociation of instructions in machine
/// combiner pass to reduce register pressure for a given BB.
@@ -1206,13 +1205,17 @@ class TargetInstrInfo : public MCInstrInfo {
/// Fix up the placeholder we may add in genAlternativeCodeSequence().
virtual void
- finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P,
+ finalizeInsInstrs(MachineInstr &Root, int &Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs) const {}
/// Return true when a code sequence can improve throughput. It
/// should be called only for instructions in loops.
/// \param Pattern - combiner pattern
- virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const;
+ virtual bool isThroughputPattern(int Pattern) const;
+
+ /// Return the objective of a combiner pattern.
+ /// \param Pattern - combiner pattern
+ virtual CombinerObjective getCombinerObjective(int Pattern) const;
/// Return true if the input \P Inst is part of a chain of dependent ops
/// that are suitable for reassociation, otherwise return false.
@@ -1256,7 +1259,7 @@ class TargetInstrInfo : public MCInstrInfo {
/// \param InstIdxForVirtReg - map of virtual register to instruction in
/// InsInstr that defines it
virtual void genAlternativeCodeSequence(
- MachineInstr &Root, MachineCombinerPattern Pattern,
+ MachineInstr &Root, int Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const;
@@ -1270,8 +1273,7 @@ class TargetInstrInfo : public MCInstrInfo {
/// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
/// reduce critical path length.
- void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
- MachineCombinerPattern Pattern,
+ void reassociateOps(MachineInstr &Root, MachineInstr &Prev, int Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
@@ -1281,8 +1283,7 @@ class TargetInstrInfo : public MCInstrInfo {
/// (new root opcode, new prev opcode) that must be used to reassociate \P
/// Root and \P Prev accoring to \P Pattern.
std::pair<unsigned, unsigned>
- getReassociationOpcodes(MachineCombinerPattern Pattern,
- const MachineInstr &Root,
+ getReassociationOpcodes(int Pattern, const MachineInstr &Root,
const MachineInstr &Prev) const;
/// The limit on resource length extension we accept in MachineCombiner Pass.
diff --git a/llvm/lib/CodeGen/MachineCombiner.cpp b/llvm/lib/CodeGen/MachineCombiner.cpp
index a4c87a7678bd8d..f30323611ca837 100644
--- a/llvm/lib/CodeGen/MachineCombiner.cpp
+++ b/llvm/lib/CodeGen/MachineCombiner.cpp
@@ -99,17 +99,16 @@ class MachineCombiner : public MachineFunctionPass {
const MachineBasicBlock &MBB);
unsigned getLatency(MachineInstr *Root, MachineInstr *NewRoot,
MachineTraceMetrics::Trace BlockTrace);
- bool
- improvesCriticalPathLen(MachineBasicBlock *MBB, MachineInstr *Root,
- MachineTraceMetrics::Trace BlockTrace,
- SmallVectorImpl<MachineInstr *> &InsInstrs,
- SmallVectorImpl<MachineInstr *> &DelInstrs,
- DenseMap<unsigned, unsigned> &InstrIdxForVirtReg,
- MachineCombinerPattern Pattern, bool SlackIsAccurate);
+ bool improvesCriticalPathLen(MachineBasicBlock *MBB, MachineInstr *Root,
+ MachineTraceMetrics::Trace BlockTrace,
+ SmallVectorImpl<MachineInstr *> &InsInstrs,
+ SmallVectorImpl<MachineInstr *> &DelInstrs,
+ DenseMap<unsigned, unsigned> &InstrIdxForVirtReg,
+ int Pattern, bool SlackIsAccurate);
bool reduceRegisterPressure(MachineInstr &Root, MachineBasicBlock *MBB,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
- MachineCombinerPattern Pattern);
+ int Pattern);
bool preservesResourceLen(MachineBasicBlock *MBB,
MachineTraceMetrics::Trace BlockTrace,
SmallVectorImpl<MachineInstr *> &InsInstrs,
@@ -123,7 +122,8 @@ class MachineCombiner : public MachineFunctionPass {
MachineTraceMetrics::Trace BlockTrace);
void verifyPatternOrder(MachineBasicBlock *MBB, MachineInstr &Root,
- SmallVector<MachineCombinerPattern, 16> &Patterns);
+ SmallVector<int, 16> &Patterns);
+ CombinerObjective getCombinerObjective(int Pattern);
};
}
@@ -290,36 +290,17 @@ unsigned MachineCombiner::getLatency(MachineInstr *Root, MachineInstr *NewRoot,
return NewRootLatency;
}
-/// The combiner's goal may differ based on which pattern it is attempting
-/// to optimize.
-enum class CombinerObjective {
- MustReduceDepth, // The data dependency chain must be improved.
- MustReduceRegisterPressure, // The register pressure must be reduced.
- Default // The critical path must not be lengthened.
-};
-
-static CombinerObjective getCombinerObjective(MachineCombinerPattern P) {
+CombinerObjective MachineCombiner::getCombinerObjective(int Pattern) {
// TODO: If C++ ever gets a real enum class, make this part of the
// MachineCombinerPattern class.
- switch (P) {
+ switch (Pattern) {
case MachineCombinerPattern::REASSOC_AX_BY:
case MachineCombinerPattern::REASSOC_AX_YB:
case MachineCombinerPattern::REASSOC_XA_BY:
case MachineCombinerPattern::REASSOC_XA_YB:
- case MachineCombinerPattern::REASSOC_XY_AMM_BMM:
- case MachineCombinerPattern::REASSOC_XMM_AMM_BMM:
- case MachineCombinerPattern::SUBADD_OP1:
- case MachineCombinerPattern::SUBADD_OP2:
- case MachineCombinerPattern::FMADD_AX:
- case MachineCombinerPattern::FMADD_XA:
- case MachineCombinerPattern::FMSUB:
- case MachineCombinerPattern::FNMSUB:
return CombinerObjective::MustReduceDepth;
- case MachineCombinerPattern::REASSOC_XY_BCA:
- case MachineCombinerPattern::REASSOC_XY_BAC:
- return CombinerObjective::MustReduceRegisterPressure;
default:
- return CombinerObjective::Default;
+ return TII->getCombinerObjective(Pattern);
}
}
@@ -349,8 +330,7 @@ std::pair<unsigned, unsigned> MachineCombiner::getLatenciesForInstrSequences(
bool MachineCombiner::reduceRegisterPressure(
MachineInstr &Root, MachineBasicBlock *MBB,
SmallVectorImpl<MachineInstr *> &InsInstrs,
- SmallVectorImpl<MachineInstr *> &DelInstrs,
- MachineCombinerPattern Pattern) {
+ SmallVectorImpl<MachineInstr *> &DelInstrs, int Pattern) {
// FIXME: for now, we don't do any check for the register pressure patterns.
// We treat them as always profitable. But we can do better if we make
// RegPressureTracker class be aware of TIE attribute. Then we can get an
@@ -368,8 +348,7 @@ bool MachineCombiner::improvesCriticalPathLen(
MachineTraceMetrics::Trace BlockTrace,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
- DenseMap<unsigned, unsigned> &InstrIdxForVirtReg,
- MachineCombinerPattern Pattern,
+ DenseMap<unsigned, unsigned> &InstrIdxForVirtReg, int Pattern,
bool SlackIsAccurate) {
// Get depth and latency of NewRoot and Root.
unsigned NewRootDepth =
@@ -493,13 +472,14 @@ bool MachineCombiner::preservesResourceLen(
/// \param Pattern is used to call target hook finalizeInsInstrs
/// \param IncrementalUpdate if true, compute instruction depths incrementally,
/// otherwise invalidate the trace
-static void insertDeleteInstructions(
- MachineBasicBlock *MBB, MachineInstr &MI,
- SmallVectorImpl<MachineInstr *> &InsInstrs,
- SmallVectorImpl<MachineInstr *> &DelInstrs,
- MachineTraceMetrics::Ensemble *TraceEnsemble,
- SparseSet<LiveRegUnit> &RegUnits, const TargetInstrInfo *TII,
- MachineCombinerPattern Pattern, bool IncrementalUpdate) {
+static void
+insertDeleteInstructions(MachineBasicBlock *MBB, MachineInstr &MI,
+ SmallVectorImpl<MachineInstr *> &InsInstrs,
+ SmallVectorImpl<MachineInstr *> &DelInstrs,
+ MachineTraceMetrics::Ensemble *TraceEnsemble,
+ SparseSet<LiveRegUnit> &RegUnits,
+ const TargetInstrInfo *TII, int Pattern,
+ bool IncrementalUpdate) {
// If we want to fix up some placeholder for some target, do it now.
// We need this because in genAlternativeCodeSequence, we have not decided the
// better pattern InsInstrs or DelInstrs, so we don't want generate some
@@ -534,9 +514,9 @@ static void insertDeleteInstructions(
// Check that the difference between original and new latency is decreasing for
// later patterns. This helps to discover sub-optimal pattern orderings.
-void MachineCombiner::verifyPatternOrder(
- MachineBasicBlock *MBB, MachineInstr &Root,
- SmallVector<MachineCombinerPattern, 16> &Patterns) {
+void MachineCombiner::verifyPatternOrder(MachineBasicBlock *MBB,
+ MachineInstr &Root,
+ SmallVector<int, 16> &Patterns) {
long PrevLatencyDiff = std::numeric_limits<long>::max();
(void)PrevLatencyDiff; // Variable is used in assert only.
for (auto P : Patterns) {
@@ -590,7 +570,7 @@ bool MachineCombiner::combineInstructions(MachineBasicBlock *MBB) {
while (BlockIter != MBB->end()) {
auto &MI = *BlockIter++;
- SmallVector<MachineCombinerPattern, 16> Patterns;
+ SmallVector<int, 16> Patterns;
// The motivating example is:
//
// MUL Other MUL_op1 MUL_op2 Other
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 9fbd516acea8e1..45710579d50df3 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -919,7 +919,7 @@ bool TargetInstrInfo::isReassociationCandidate(const MachineInstr &Inst,
// instruction is known to not increase the critical path, then don't match
// that pattern.
bool TargetInstrInfo::getMachineCombinerPatterns(
- MachineInstr &Root, SmallVectorImpl<MachineCombinerPattern> &Patterns,
+ MachineInstr &Root, SmallVectorImpl<int> &Patterns,
bool DoRegPressureReduce) const {
bool Commute;
if (isReassociationCandidate(Root, Commute)) {
@@ -941,14 +941,14 @@ bool TargetInstrInfo::getMachineCombinerPatterns(
}
/// Return true when a code sequence can improve loop throughput.
-bool
-TargetInstrInfo::isThroughputPattern(MachineCombinerPattern Pattern) const {
- return false;
+bool TargetInstrInfo::isThroughputPattern(int Pattern) const { return false; }
+
+CombinerObjective TargetInstrInfo::getCombinerObjective(int Pattern) const {
+ return CombinerObjective::Default;
}
std::pair<unsigned, unsigned>
-TargetInstrInfo::getReassociationOpcodes(MachineCombinerPattern Pattern,
- const MachineInstr &Root,
+TargetInstrInfo::getReassociationOpcodes(int Pattern, const MachineInstr &Root,
const MachineInstr &Prev) const {
bool AssocCommutRoot = isAssociativeAndCommutative(Root);
bool AssocCommutPrev = isAssociativeAndCommutative(Prev);
@@ -1036,7 +1036,7 @@ TargetInstrInfo::getReassociationOpcodes(MachineCombinerPattern Pattern,
// Return a pair of boolean flags showing if the new root and new prev operands
// must be swapped. See visual example of the rule in
// TargetInstrInfo::getReassociationOpcodes.
-static std::pair<bool, bool> mustSwapOperands(MachineCombinerPattern Pattern) {
+static std::pair<bool, bool> mustSwapOperands(int Pattern) {
switch (Pattern) {
default:
llvm_unreachable("Unexpected pattern");
@@ -1054,8 +1054,7 @@ static std::pair<bool, bool> mustSwapOperands(MachineCombinerPattern Pattern) {
/// Attempt the reassociation transformation to reduce critical path length.
/// See the above comments before getMachineCombinerPatterns().
void TargetInstrInfo::reassociateOps(
- MachineInstr &Root, MachineInstr &Prev,
- MachineCombinerPattern Pattern,
+ MachineInstr &Root, MachineInstr &Prev, int Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
@@ -1177,8 +1176,7 @@ void TargetInstrInfo::reassociateOps(
}
void TargetInstrInfo::genAlternativeCodeSequence(
- MachineInstr &Root, MachineCombinerPattern Pattern,
- SmallVectorImpl<MachineInstr *> &InsInstrs,
+ MachineInstr &Root, int Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const {
MachineRegisterInfo &MRI = Root.getMF()->getRegInfo();
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 22687b0e31c284..ac7710bfd05ca4 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -6056,7 +6056,7 @@ bool AArch64InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst,
/// Find instructions that can be turned into madd.
static bool getMaddPatterns(MachineInstr &Root,
- SmallVectorImpl<MachineCombinerPattern> &Patterns) {
+ SmallVectorImpl<int> &Patterns) {
unsigned Opc = Root.getOpcode();
MachineBasicBlock &MBB = *Root.getParent();
bool Found = false;
@@ -6076,22 +6076,21 @@ static bool getMaddPatterns(MachineInstr &Root,
Opc = NewOpc;
}
- auto setFound = [&](int Opcode, int Operand, unsigned ZeroReg,
- MachineCombinerPattern Pattern) {
+ auto setFound = [&](int Opcode, int Operand, unsigned ZeroReg, int Pattern) {
if (canCombineWithMUL(MBB, Root.getOperand(Operand), Opcode, ZeroReg)) {
Patterns.push_back(Pattern);
Found = true;
}
};
- auto setVFound = [&](int Opcode,...
[truncated]
|
|
@llvm/pr-subscribers-backend-risc-v Author: Pengcheng Wang (wangpc-pp) ChangesWe split target-dependent MachineCombiner patterns to their target This makes MachineCombiner much more target-independent. Patch is 108.59 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/87991.diff 12 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/MachineCombinerPattern.h b/llvm/include/llvm/CodeGen/MachineCombinerPattern.h
index 89eed7463bd783..ed87667662663a 100644
--- a/llvm/include/llvm/CodeGen/MachineCombinerPattern.h
+++ b/llvm/include/llvm/CodeGen/MachineCombinerPattern.h
@@ -16,8 +16,16 @@
namespace llvm {
+/// The combiner's goal may differ based on which pattern it is attempting
+/// to optimize.
+enum class CombinerObjective {
+ MustReduceDepth, // The data dependency chain must be improved.
+ MustReduceRegisterPressure, // The register pressure must be reduced.
+ Default // The critical path must not be lengthened.
+};
+
/// These are instruction patterns matched by the machine combiner pass.
-enum class MachineCombinerPattern {
+enum MachineCombinerPattern {
// These are commutative variants for reassociating a computation chain. See
// the comments before getMachineCombinerPatterns() in TargetInstrInfo.cpp.
REASSOC_AX_BY,
@@ -25,161 +33,7 @@ enum class MachineCombinerPattern {
REASSOC_XA_BY,
REASSOC_XA_YB,
- // These are patterns matched by the PowerPC to reassociate FMA chains.
- REASSOC_XY_AMM_BMM,
- REASSOC_XMM_AMM_BMM,
-
- // These are patterns matched by the PowerPC to reassociate FMA and FSUB to
- // reduce register pressure.
- REASSOC_XY_BCA,
- REASSOC_XY_BAC,
-
- // These are patterns used to reduce the length of dependence chain.
- SUBADD_OP1,
- SUBADD_OP2,
-
- // These are multiply-add patterns matched by the AArch64 machine combiner.
- MULADDW_OP1,
- MULADDW_OP2,
- MULSUBW_OP1,
- MULSUBW_OP2,
- MULADDWI_OP1,
- MULSUBWI_OP1,
- MULADDX_OP1,
- MULADDX_OP2,
- MULSUBX_OP1,
- MULSUBX_OP2,
- MULADDXI_OP1,
- MULSUBXI_OP1,
- // NEON integers vectors
- MULADDv8i8_OP1,
- MULADDv8i8_OP2,
- MULADDv16i8_OP1,
- MULADDv16i8_OP2,
- MULADDv4i16_OP1,
- MULADDv4i16_OP2,
- MULADDv8i16_OP1,
- MULADDv8i16_OP2,
- MULADDv2i32_OP1,
- MULADDv2i32_OP2,
- MULADDv4i32_OP1,
- MULADDv4i32_OP2,
-
- MULSUBv8i8_OP1,
- MULSUBv8i8_OP2,
- MULSUBv16i8_OP1,
- MULSUBv16i8_OP2,
- MULSUBv4i16_OP1,
- MULSUBv4i16_OP2,
- MULSUBv8i16_OP1,
- MULSUBv8i16_OP2,
- MULSUBv2i32_OP1,
- MULSUBv2i32_OP2,
- MULSUBv4i32_OP1,
- MULSUBv4i32_OP2,
-
- MULADDv4i16_indexed_OP1,
- MULADDv4i16_indexed_OP2,
- MULADDv8i16_indexed_OP1,
- MULADDv8i16_indexed_OP2,
- MULADDv2i32_indexed_OP1,
- MULADDv2i32_indexed_OP2,
- MULADDv4i32_indexed_OP1,
- MULADDv4i32_indexed_OP2,
-
- MULSUBv4i16_indexed_OP1,
- MULSUBv4i16_indexed_OP2,
- MULSUBv8i16_indexed_OP1,
- MULSUBv8i16_indexed_OP2,
- MULSUBv2i32_indexed_OP1,
- MULSUBv2i32_indexed_OP2,
- MULSUBv4i32_indexed_OP1,
- MULSUBv4i32_indexed_OP2,
-
- // Floating Point
- FMULADDH_OP1,
- FMULADDH_OP2,
- FMULSUBH_OP1,
- FMULSUBH_OP2,
- FMULADDS_OP1,
- FMULADDS_OP2,
- FMULSUBS_OP1,
- FMULSUBS_OP2,
- FMULADDD_OP1,
- FMULADDD_OP2,
- FMULSUBD_OP1,
- FMULSUBD_OP2,
- FNMULSUBH_OP1,
- FNMULSUBS_OP1,
- FNMULSUBD_OP1,
- FMLAv1i32_indexed_OP1,
- FMLAv1i32_indexed_OP2,
- FMLAv1i64_indexed_OP1,
- FMLAv1i64_indexed_OP2,
- FMLAv4f16_OP1,
- FMLAv4f16_OP2,
- FMLAv8f16_OP1,
- FMLAv8f16_OP2,
- FMLAv2f32_OP2,
- FMLAv2f32_OP1,
- FMLAv2f64_OP1,
- FMLAv2f64_OP2,
- FMLAv4i16_indexed_OP1,
- FMLAv4i16_indexed_OP2,
- FMLAv8i16_indexed_OP1,
- FMLAv8i16_indexed_OP2,
- FMLAv2i32_indexed_OP1,
- FMLAv2i32_indexed_OP2,
- FMLAv2i64_indexed_OP1,
- FMLAv2i64_indexed_OP2,
- FMLAv4f32_OP1,
- FMLAv4f32_OP2,
- FMLAv4i32_indexed_OP1,
- FMLAv4i32_indexed_OP2,
- FMLSv1i32_indexed_OP2,
- FMLSv1i64_indexed_OP2,
- FMLSv4f16_OP1,
- FMLSv4f16_OP2,
- FMLSv8f16_OP1,
- FMLSv8f16_OP2,
- FMLSv2f32_OP1,
- FMLSv2f32_OP2,
- FMLSv2f64_OP1,
- FMLSv2f64_OP2,
- FMLSv4i16_indexed_OP1,
- FMLSv4i16_indexed_OP2,
- FMLSv8i16_indexed_OP1,
- FMLSv8i16_indexed_OP2,
- FMLSv2i32_indexed_OP1,
- FMLSv2i32_indexed_OP2,
- FMLSv2i64_indexed_OP1,
- FMLSv2i64_indexed_OP2,
- FMLSv4f32_OP1,
- FMLSv4f32_OP2,
- FMLSv4i32_indexed_OP1,
- FMLSv4i32_indexed_OP2,
-
- FMULv2i32_indexed_OP1,
- FMULv2i32_indexed_OP2,
- FMULv2i64_indexed_OP1,
- FMULv2i64_indexed_OP2,
- FMULv4i16_indexed_OP1,
- FMULv4i16_indexed_OP2,
- FMULv4i32_indexed_OP1,
- FMULv4i32_indexed_OP2,
- FMULv8i16_indexed_OP1,
- FMULv8i16_indexed_OP2,
-
- // RISCV FMADD, FMSUB, FNMSUB patterns
- FMADD_AX,
- FMADD_XA,
- FMSUB,
- FNMSUB,
-
- // X86 VNNI
- DPWSSD,
-
- FNMADD,
+ TARGET_PATTERN_START
};
} // end namespace llvm
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 9fd0ebe6956fbe..658092e192dd33 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -19,6 +19,7 @@
#include "llvm/ADT/Uniformity.h"
#include "llvm/CodeGen/MIRFormatter.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineCombinerPattern.h"
#include "llvm/CodeGen/MachineCycleAnalysis.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
@@ -61,7 +62,6 @@ class TargetRegisterClass;
class TargetRegisterInfo;
class TargetSchedModel;
class TargetSubtargetInfo;
-enum class MachineCombinerPattern;
enum class MachineTraceStrategy;
template <class T> class SmallVectorImpl;
@@ -1191,10 +1191,9 @@ class TargetInstrInfo : public MCInstrInfo {
/// faster sequence.
/// \param Root - Instruction that could be combined with one of its operands
/// \param Patterns - Vector of possible combination patterns
- virtual bool
- getMachineCombinerPatterns(MachineInstr &Root,
- SmallVectorImpl<MachineCombinerPattern> &Patterns,
- bool DoRegPressureReduce) const;
+ virtual bool getMachineCombinerPatterns(MachineInstr &Root,
+ SmallVectorImpl<int> &Patterns,
+ bool DoRegPressureReduce) const;
/// Return true if target supports reassociation of instructions in machine
/// combiner pass to reduce register pressure for a given BB.
@@ -1206,13 +1205,17 @@ class TargetInstrInfo : public MCInstrInfo {
/// Fix up the placeholder we may add in genAlternativeCodeSequence().
virtual void
- finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P,
+ finalizeInsInstrs(MachineInstr &Root, int &Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs) const {}
/// Return true when a code sequence can improve throughput. It
/// should be called only for instructions in loops.
/// \param Pattern - combiner pattern
- virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const;
+ virtual bool isThroughputPattern(int Pattern) const;
+
+ /// Return the objective of a combiner pattern.
+ /// \param Pattern - combiner pattern
+ virtual CombinerObjective getCombinerObjective(int Pattern) const;
/// Return true if the input \P Inst is part of a chain of dependent ops
/// that are suitable for reassociation, otherwise return false.
@@ -1256,7 +1259,7 @@ class TargetInstrInfo : public MCInstrInfo {
/// \param InstIdxForVirtReg - map of virtual register to instruction in
/// InsInstr that defines it
virtual void genAlternativeCodeSequence(
- MachineInstr &Root, MachineCombinerPattern Pattern,
+ MachineInstr &Root, int Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const;
@@ -1270,8 +1273,7 @@ class TargetInstrInfo : public MCInstrInfo {
/// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
/// reduce critical path length.
- void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
- MachineCombinerPattern Pattern,
+ void reassociateOps(MachineInstr &Root, MachineInstr &Prev, int Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
@@ -1281,8 +1283,7 @@ class TargetInstrInfo : public MCInstrInfo {
/// (new root opcode, new prev opcode) that must be used to reassociate \P
/// Root and \P Prev accoring to \P Pattern.
std::pair<unsigned, unsigned>
- getReassociationOpcodes(MachineCombinerPattern Pattern,
- const MachineInstr &Root,
+ getReassociationOpcodes(int Pattern, const MachineInstr &Root,
const MachineInstr &Prev) const;
/// The limit on resource length extension we accept in MachineCombiner Pass.
diff --git a/llvm/lib/CodeGen/MachineCombiner.cpp b/llvm/lib/CodeGen/MachineCombiner.cpp
index a4c87a7678bd8d..f30323611ca837 100644
--- a/llvm/lib/CodeGen/MachineCombiner.cpp
+++ b/llvm/lib/CodeGen/MachineCombiner.cpp
@@ -99,17 +99,16 @@ class MachineCombiner : public MachineFunctionPass {
const MachineBasicBlock &MBB);
unsigned getLatency(MachineInstr *Root, MachineInstr *NewRoot,
MachineTraceMetrics::Trace BlockTrace);
- bool
- improvesCriticalPathLen(MachineBasicBlock *MBB, MachineInstr *Root,
- MachineTraceMetrics::Trace BlockTrace,
- SmallVectorImpl<MachineInstr *> &InsInstrs,
- SmallVectorImpl<MachineInstr *> &DelInstrs,
- DenseMap<unsigned, unsigned> &InstrIdxForVirtReg,
- MachineCombinerPattern Pattern, bool SlackIsAccurate);
+ bool improvesCriticalPathLen(MachineBasicBlock *MBB, MachineInstr *Root,
+ MachineTraceMetrics::Trace BlockTrace,
+ SmallVectorImpl<MachineInstr *> &InsInstrs,
+ SmallVectorImpl<MachineInstr *> &DelInstrs,
+ DenseMap<unsigned, unsigned> &InstrIdxForVirtReg,
+ int Pattern, bool SlackIsAccurate);
bool reduceRegisterPressure(MachineInstr &Root, MachineBasicBlock *MBB,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
- MachineCombinerPattern Pattern);
+ int Pattern);
bool preservesResourceLen(MachineBasicBlock *MBB,
MachineTraceMetrics::Trace BlockTrace,
SmallVectorImpl<MachineInstr *> &InsInstrs,
@@ -123,7 +122,8 @@ class MachineCombiner : public MachineFunctionPass {
MachineTraceMetrics::Trace BlockTrace);
void verifyPatternOrder(MachineBasicBlock *MBB, MachineInstr &Root,
- SmallVector<MachineCombinerPattern, 16> &Patterns);
+ SmallVector<int, 16> &Patterns);
+ CombinerObjective getCombinerObjective(int Pattern);
};
}
@@ -290,36 +290,17 @@ unsigned MachineCombiner::getLatency(MachineInstr *Root, MachineInstr *NewRoot,
return NewRootLatency;
}
-/// The combiner's goal may differ based on which pattern it is attempting
-/// to optimize.
-enum class CombinerObjective {
- MustReduceDepth, // The data dependency chain must be improved.
- MustReduceRegisterPressure, // The register pressure must be reduced.
- Default // The critical path must not be lengthened.
-};
-
-static CombinerObjective getCombinerObjective(MachineCombinerPattern P) {
+CombinerObjective MachineCombiner::getCombinerObjective(int Pattern) {
// TODO: If C++ ever gets a real enum class, make this part of the
// MachineCombinerPattern class.
- switch (P) {
+ switch (Pattern) {
case MachineCombinerPattern::REASSOC_AX_BY:
case MachineCombinerPattern::REASSOC_AX_YB:
case MachineCombinerPattern::REASSOC_XA_BY:
case MachineCombinerPattern::REASSOC_XA_YB:
- case MachineCombinerPattern::REASSOC_XY_AMM_BMM:
- case MachineCombinerPattern::REASSOC_XMM_AMM_BMM:
- case MachineCombinerPattern::SUBADD_OP1:
- case MachineCombinerPattern::SUBADD_OP2:
- case MachineCombinerPattern::FMADD_AX:
- case MachineCombinerPattern::FMADD_XA:
- case MachineCombinerPattern::FMSUB:
- case MachineCombinerPattern::FNMSUB:
return CombinerObjective::MustReduceDepth;
- case MachineCombinerPattern::REASSOC_XY_BCA:
- case MachineCombinerPattern::REASSOC_XY_BAC:
- return CombinerObjective::MustReduceRegisterPressure;
default:
- return CombinerObjective::Default;
+ return TII->getCombinerObjective(Pattern);
}
}
@@ -349,8 +330,7 @@ std::pair<unsigned, unsigned> MachineCombiner::getLatenciesForInstrSequences(
bool MachineCombiner::reduceRegisterPressure(
MachineInstr &Root, MachineBasicBlock *MBB,
SmallVectorImpl<MachineInstr *> &InsInstrs,
- SmallVectorImpl<MachineInstr *> &DelInstrs,
- MachineCombinerPattern Pattern) {
+ SmallVectorImpl<MachineInstr *> &DelInstrs, int Pattern) {
// FIXME: for now, we don't do any check for the register pressure patterns.
// We treat them as always profitable. But we can do better if we make
// RegPressureTracker class be aware of TIE attribute. Then we can get an
@@ -368,8 +348,7 @@ bool MachineCombiner::improvesCriticalPathLen(
MachineTraceMetrics::Trace BlockTrace,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
- DenseMap<unsigned, unsigned> &InstrIdxForVirtReg,
- MachineCombinerPattern Pattern,
+ DenseMap<unsigned, unsigned> &InstrIdxForVirtReg, int Pattern,
bool SlackIsAccurate) {
// Get depth and latency of NewRoot and Root.
unsigned NewRootDepth =
@@ -493,13 +472,14 @@ bool MachineCombiner::preservesResourceLen(
/// \param Pattern is used to call target hook finalizeInsInstrs
/// \param IncrementalUpdate if true, compute instruction depths incrementally,
/// otherwise invalidate the trace
-static void insertDeleteInstructions(
- MachineBasicBlock *MBB, MachineInstr &MI,
- SmallVectorImpl<MachineInstr *> &InsInstrs,
- SmallVectorImpl<MachineInstr *> &DelInstrs,
- MachineTraceMetrics::Ensemble *TraceEnsemble,
- SparseSet<LiveRegUnit> &RegUnits, const TargetInstrInfo *TII,
- MachineCombinerPattern Pattern, bool IncrementalUpdate) {
+static void
+insertDeleteInstructions(MachineBasicBlock *MBB, MachineInstr &MI,
+ SmallVectorImpl<MachineInstr *> &InsInstrs,
+ SmallVectorImpl<MachineInstr *> &DelInstrs,
+ MachineTraceMetrics::Ensemble *TraceEnsemble,
+ SparseSet<LiveRegUnit> &RegUnits,
+ const TargetInstrInfo *TII, int Pattern,
+ bool IncrementalUpdate) {
// If we want to fix up some placeholder for some target, do it now.
// We need this because in genAlternativeCodeSequence, we have not decided the
// better pattern InsInstrs or DelInstrs, so we don't want generate some
@@ -534,9 +514,9 @@ static void insertDeleteInstructions(
// Check that the difference between original and new latency is decreasing for
// later patterns. This helps to discover sub-optimal pattern orderings.
-void MachineCombiner::verifyPatternOrder(
- MachineBasicBlock *MBB, MachineInstr &Root,
- SmallVector<MachineCombinerPattern, 16> &Patterns) {
+void MachineCombiner::verifyPatternOrder(MachineBasicBlock *MBB,
+ MachineInstr &Root,
+ SmallVector<int, 16> &Patterns) {
long PrevLatencyDiff = std::numeric_limits<long>::max();
(void)PrevLatencyDiff; // Variable is used in assert only.
for (auto P : Patterns) {
@@ -590,7 +570,7 @@ bool MachineCombiner::combineInstructions(MachineBasicBlock *MBB) {
while (BlockIter != MBB->end()) {
auto &MI = *BlockIter++;
- SmallVector<MachineCombinerPattern, 16> Patterns;
+ SmallVector<int, 16> Patterns;
// The motivating example is:
//
// MUL Other MUL_op1 MUL_op2 Other
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 9fbd516acea8e1..45710579d50df3 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -919,7 +919,7 @@ bool TargetInstrInfo::isReassociationCandidate(const MachineInstr &Inst,
// instruction is known to not increase the critical path, then don't match
// that pattern.
bool TargetInstrInfo::getMachineCombinerPatterns(
- MachineInstr &Root, SmallVectorImpl<MachineCombinerPattern> &Patterns,
+ MachineInstr &Root, SmallVectorImpl<int> &Patterns,
bool DoRegPressureReduce) const {
bool Commute;
if (isReassociationCandidate(Root, Commute)) {
@@ -941,14 +941,14 @@ bool TargetInstrInfo::getMachineCombinerPatterns(
}
/// Return true when a code sequence can improve loop throughput.
-bool
-TargetInstrInfo::isThroughputPattern(MachineCombinerPattern Pattern) const {
- return false;
+bool TargetInstrInfo::isThroughputPattern(int Pattern) const { return false; }
+
+CombinerObjective TargetInstrInfo::getCombinerObjective(int Pattern) const {
+ return CombinerObjective::Default;
}
std::pair<unsigned, unsigned>
-TargetInstrInfo::getReassociationOpcodes(MachineCombinerPattern Pattern,
- const MachineInstr &Root,
+TargetInstrInfo::getReassociationOpcodes(int Pattern, const MachineInstr &Root,
const MachineInstr &Prev) const {
bool AssocCommutRoot = isAssociativeAndCommutative(Root);
bool AssocCommutPrev = isAssociativeAndCommutative(Prev);
@@ -1036,7 +1036,7 @@ TargetInstrInfo::getReassociationOpcodes(MachineCombinerPattern Pattern,
// Return a pair of boolean flags showing if the new root and new prev operands
// must be swapped. See visual example of the rule in
// TargetInstrInfo::getReassociationOpcodes.
-static std::pair<bool, bool> mustSwapOperands(MachineCombinerPattern Pattern) {
+static std::pair<bool, bool> mustSwapOperands(int Pattern) {
switch (Pattern) {
default:
llvm_unreachable("Unexpected pattern");
@@ -1054,8 +1054,7 @@ static std::pair<bool, bool> mustSwapOperands(MachineCombinerPattern Pattern) {
/// Attempt the reassociation transformation to reduce critical path length.
/// See the above comments before getMachineCombinerPatterns().
void TargetInstrInfo::reassociateOps(
- MachineInstr &Root, MachineInstr &Prev,
- MachineCombinerPattern Pattern,
+ MachineInstr &Root, MachineInstr &Prev, int Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
@@ -1177,8 +1176,7 @@ void TargetInstrInfo::reassociateOps(
}
void TargetInstrInfo::genAlternativeCodeSequence(
- MachineInstr &Root, MachineCombinerPattern Pattern,
- SmallVectorImpl<MachineInstr *> &InsInstrs,
+ MachineInstr &Root, int Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const {
MachineRegisterInfo &MRI = Root.getMF()->getRegInfo();
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 22687b0e31c284..ac7710bfd05ca4 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -6056,7 +6056,7 @@ bool AArch64InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst,
/// Find instructions that can be turned into madd.
static bool getMaddPatterns(MachineInstr &Root,
- SmallVectorImpl<MachineCombinerPattern> &Patterns) {
+ SmallVectorImpl<int> &Patterns) {
unsigned Opc = Root.getOpcode();
MachineBasicBlock &MBB = *Root.getParent();
bool Found = false;
@@ -6076,22 +6076,21 @@ static bool getMaddPatterns(MachineInstr &Root,
Opc = NewOpc;
}
- auto setFound = [&](int Opcode, int Operand, unsigned ZeroReg,
- MachineCombinerPattern Pattern) {
+ auto setFound = [&](int Opcode, int Operand, unsigned ZeroReg, int Pattern) {
if (canCombineWithMUL(MBB, Root.getOperand(Operand), Opcode, ZeroReg)) {
Patterns.push_back(Pattern);
Found = true;
}
};
- auto setVFound = [&](int Opcode,...
[truncated]
|
wangpc-pp
requested review from
asi-sc,
lukel97,
topperc,
LuoYuanke,
rotateright and
asavonic
mshockwave
reviewed
Apr 8, 2024
Created using spr 1.3.6-beta.1
|
✅ With the latest revision this PR passed the C/C++ code formatter. |
Created using spr 1.3.6-beta.1
wangpc-pp
deleted the
users/wangpc-pp/spr/machinecombinernfc-split-target-dependent-patterns
branch
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
We split target-dependent MachineCombiner patterns into their target
folder.
This makes MachineCombiner much more target-independent.