[SPIR-V] Map llvm.{min,max}num to GL::N{Min,Max} #88009
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SPIR-V intsruction selection was mapping the LLVM min/max instrinsics to FMin and FMax respectively for GL/Vulkan environments, which does not match the intrinsic's documented treatment of NaN operands. This patch switches the mapping to the correctly matched NMin and NMax operations. Fixes llvm#87072
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@llvm/pr-subscribers-backend-spir-v Author: Natalie Chouinard (sudonatalie) ChangesSPIR-V intsruction selection was mapping the LLVM float min/max intrinsics to FMin and FMax respectively for GL/Vulkan environments, which does not match the intrinsics' documented treatment of NaN operands. This patch switches the mapping to the correctly matched NMin and NMax operations. Fixes #87072 Full diff: https://github.com/llvm/llvm-project/pull/88009.diff 3 Files Affected:
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 49749b56345306..45a70da7f86902 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -432,10 +432,10 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg,
case TargetOpcode::G_FMINNUM:
case TargetOpcode::G_FMINIMUM:
- return selectExtInst(ResVReg, ResType, I, CL::fmin, GL::FMin);
+ return selectExtInst(ResVReg, ResType, I, CL::fmin, GL::NMin);
case TargetOpcode::G_FMAXNUM:
case TargetOpcode::G_FMAXIMUM:
- return selectExtInst(ResVReg, ResType, I, CL::fmax, GL::FMax);
+ return selectExtInst(ResVReg, ResType, I, CL::fmax, GL::NMax);
case TargetOpcode::G_FCOPYSIGN:
return selectExtInst(ResVReg, ResType, I, CL::copysign);
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmax.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmax.ll
index 48e916581f9ff2..8cad0e20e5156d 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmax.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmax.ll
@@ -5,21 +5,21 @@
define noundef half @test_fmax_half(half noundef %a, half noundef %b) {
entry:
-; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] FMax %[[#]] %[[#]]
+; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] NMax %[[#]] %[[#]]
%0 = call half @llvm.maxnum.f16(half %a, half %b)
ret half %0
}
define noundef float @test_fmax_float(float noundef %a, float noundef %b) {
entry:
-; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] FMax %[[#]] %[[#]]
+; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] NMax %[[#]] %[[#]]
%0 = call float @llvm.maxnum.f32(float %a, float %b)
ret float %0
}
define noundef double @test_fmax_double(double noundef %a, double noundef %b) {
entry:
-; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] FMax %[[#]] %[[#]]
+; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] NMax %[[#]] %[[#]]
%0 = call double @llvm.maxnum.f64(double %a, double %b)
ret double %0
}
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmin.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmin.ll
index 5bfd69c972a3fa..fa2fceb5f63687 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmin.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmin.ll
@@ -7,21 +7,21 @@
define noundef half @test_fmax_half(half noundef %a, half noundef %b) {
entry:
-; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] FMin %[[#]] %[[#]]
+; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] NMin %[[#]] %[[#]]
%0 = call half @llvm.minnum.f16(half %a, half %b)
ret half %0
}
define noundef float @test_fmax_float(float noundef %a, float noundef %b) {
entry:
-; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] FMin %[[#]] %[[#]]
+; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] NMin %[[#]] %[[#]]
%0 = call float @llvm.minnum.f32(float %a, float %b)
ret float %0
}
define noundef double @test_fmax_double(double noundef %a, double noundef %b) {
entry:
-; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] FMin %[[#]] %[[#]]
+; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] NMin %[[#]] %[[#]]
%0 = call double @llvm.minnum.f64(double %a, double %b)
ret double %0
}
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farzonl
reviewed
Apr 8, 2024
farzonl
reviewed
Apr 8, 2024
|
LGTM. Thanks for picking this up. |
farzonl
approved these changes
Apr 8, 2024
farzonl
reviewed
Apr 8, 2024
| @@ -432,10 +432,10 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg, | |||
|
|
|||
| case TargetOpcode::G_FMINNUM: | |||
| case TargetOpcode::G_FMINIMUM: | |||
| return selectExtInst(ResVReg, ResType, I, CL::fmin, GL::FMin); | |||
| return selectExtInst(ResVReg, ResType, I, CL::fmin, GL::NMin); | |||
There was a problem hiding this comment.
I'm a little suprised there were no other tests that needed to be updated than the ones I added.
michalpaszkowski
approved these changes
Apr 8, 2024
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SPIR-V intsruction selection was mapping the LLVM float min/max intrinsics to FMin and FMax respectively for GL/Vulkan environments, which does not match the intrinsics' documented treatment of NaN operands. This patch switches the mapping to the correctly matched NMin and NMax operations.
Fixes #87072