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[SDAG] Apply or-disjoint in SelectionDAG::isBaseWithConstantOffset #88493
[SDAG] Apply or-disjoint in SelectionDAG::isBaseWithConstantOffset #88493
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@llvm/pr-subscribers-llvm-selectiondag Author: fengfeng (fengfeng09) ChangesOr-disjoint application. Full diff: https://github.com/llvm/llvm-project/pull/88493.diff 2 Files Affected:
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 1dd0fa49a460f8..67feb47fef076f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5191,6 +5191,9 @@ bool SelectionDAG::isADDLike(SDValue Op) const {
}
bool SelectionDAG::isBaseWithConstantOffset(SDValue Op) const {
+ if (isADDLike(Op) && isa<ConstantSDNode>(Op.getOperand(1)))
+ return true;
+
if ((Op.getOpcode() != ISD::ADD && Op.getOpcode() != ISD::OR) ||
!isa<ConstantSDNode>(Op.getOperand(1)))
return false;
diff --git a/llvm/test/CodeGen/AVR/base-with-add-like-constant-offset.ll b/llvm/test/CodeGen/AVR/base-with-add-like-constant-offset.ll
new file mode 100644
index 00000000000000..6077f71b5efe06
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/base-with-add-like-constant-offset.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -mtriple=avr %s -start-before=avr-isel -o - -stop-after=avr-isel | FileCheck %s
+
+define void @test(i16 %x, ptr addrspace(1) %o) {
+ ; CHECK-LABEL: name: test
+ ; CHECK: bb.0 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $r25r24, $r23r22
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:dregs = COPY $r23r22
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:dregs = COPY $r25r24
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:ptrdispregs = COPY [[COPY]]
+ ; CHECK-NEXT: STDWPtrQRr [[COPY2]], 10, [[COPY1]] :: (store (s16) into %ir.addr, align 1, addrspace 1)
+ ; CHECK-NEXT: RET implicit $r1
+ %int = ptrtoint ptr addrspace(1) %o to i16
+ %or = or disjoint i16 %int, 10
+ %addr = inttoptr i16 %or to ptr addrspace(1)
+ store i16 %x, ptr addrspace(1) %addr
+ ret void
+}
+
|
@@ -5191,6 +5191,9 @@ bool SelectionDAG::isADDLike(SDValue Op) const { | |||
} | |||
|
|||
bool SelectionDAG::isBaseWithConstantOffset(SDValue Op) const { |
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Can we not just simplify this function to:
bool SelectionDAG::isBaseWithConstantOffset(SDValue Op) const {
return (Op.getOpcode() == ISD::ADD || isADDLike(Op)) &&
isa<ConstantSDNode>(Op.getOperand(1));
}
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Good suggestion.
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LGTM
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Title should be improved, it is missing any context
return false; | ||
|
||
return true; | ||
return (Op.getOpcode() == ISD::ADD || isADDLike(Op)) && |
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This can call computeKnownBits on both operands an OR that doesn't have a constant right hand side. Is there better way to do that with the cheap constant right hand side check first?
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Sure.
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return false; | ||
|
||
return true; | ||
return isa<ConstantSDNode>(Op.getOperand(1)) && |
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This will crash if the node doesn't have a second operand.
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LG
Signed-off-by: feng.feng <feng.feng@iluvatar.com>
If the addr base of a Load/Store Inst is an Or-disjoint with a constant, it could be selected to an MI with constans offset if the target have. Signed-off-by: feng.feng <feng.feng@iluvatar.com>
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I have no write access to the repo,could someone help me to merge this PR? |
@fengfeng09 Congratulations on having your first Pull Request (PR) merged into the LLVM Project! Your changes will be combined with recent changes from other authors, then tested Please check whether problems have been caused by your change specifically, as How to do this, and the rest of the post-merge process, is covered in detail here. If your change does cause a problem, it may be reverted, or you can revert it yourself. If you don't get any reports, no action is required from you. Your changes are working as expected, well done! |
…lvm#88493) Signed-off-by: feng.feng <feng.feng@iluvatar.com>
…lvm#88493) Signed-off-by: feng.feng <feng.feng@iluvatar.com>
Or-disjoint application.