[llvm-exegesis] Add support for alder lake

[boomanaiden154]

This patch adds the PFM counter definitions for Intel alder lake CPUs.

[llvmbot]

@llvm/pr-subscribers-backend-x86

Author: Aiden Grossman (boomanaiden154)

Changes

This patch adds the PFM counter definitions for Intel alder lake CPUs.

---

Full diff: https://github.com/llvm/llvm-project/pull/88967.diff

1 Files Affected:

• (modified) llvm/lib/Target/X86/X86PfmCounters.td (+21)

diff --git a/llvm/lib/Target/X86/X86PfmCounters.td b/llvm/lib/Target/X86/X86PfmCounters.td
index d87a559aa353b1..11846477e64ae0 100644
--- a/llvm/lib/Target/X86/X86PfmCounters.td
+++ b/llvm/lib/Target/X86/X86PfmCounters.td
@@ -204,6 +204,27 @@ def : PfmCountersBinding<"icelake-server", IceLakePfmCounters>;
 def : PfmCountersBinding<"rocketlake", IceLakePfmCounters>;
 def : PfmCountersBinding<"tigerlake", IceLakePfmCounters>;
 
+def AlderLakePfmCounters : ProcPfmCounters {
+  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
+  let UopsCounter = UopsIssuedPfmCounter;
+  let IssueCounters = [
+    PfmIssueCounter<"ADLPPort00", "uops_dispatched_port:port_0">,
+    PfmIssueCounter<"ADLPPort01", "uops_dispatched_port:port_1">,
+    PfmIssueCounter<"ADLPPort02", "uops_dispatched_port:port_2_3_10">,
+    PfmIssueCounter<"ADLPPort03", "uops_dispatched_port:port_2_3_10">,
+    PfmIssueCounter<"ADLPPort04", "uops_dispatched_port:port_4_9">,
+    PfmIssueCounter<"ADLPPort05", "uops_dispatched_port:port_5_11">,
+    PfmIssueCounter<"ADLPPort06", "uops_dispatched_port:port_6">,
+    PfmIssueCounter<"ADLPPort07", "uops_dispatched_port:port_7_8">,
+    PfmIssueCounter<"ADLPPort08", "uops_dispatched_port:port_7_8">,
+    PfmIssueCounter<"ADLPPort09", "uops_dispatched_port:port_4_9">,
+    PfmIssueCounter<"ADLPPort10", "uops_dispatched_port:port_2_3_10">,
+    PfmIssueCounter<"ADLPPort11", "uops_dispatched_port:port_5_11">,
+  ];
+  let ValidationCounters = DefaultIntelPfmValidationCounters;
+}
+def : PfmCountersBinding<"alderlake", AlderLakePfmCounters>;
+
 // AMD X86 Counters.
 defvar DefaultAMDPfmValidationCounters = [
   PfmValidationCounter<InstructionRetired, "RETIRED_INSTRUCTIONS">,

[boomanaiden154]

From what I understand, LLVM just reports the microarch as alder lake for both golden cove and gracemont. Not sure this will end up being a large issue as cycles measurements should be the same between both and uops measurements aren't possible on gracemont.

I also don't have access to any alder lake hardware, so I can't test this, but it should work. I've checked all the counter definitions against what exists in libpfm (at least tip of tree libpfm).

[RKSimon]

Can you map to the composite ports instead or repeating them?

What options do we have to hint to llvm-exegesis what CPU mask to allow?

[boomanaiden154]

Can you map to the composite ports instead or repeating them?

It doesn't look like any of the composite ports actually map directly to the counters?

What options do we have to hint to llvm-exegesis what CPU mask to allow?

Can you clarify what you mean by this? As in differentiating between different microarchitectures on the same platform? I don't believe there is any support for doing that currently. There also isn't any support for CPU affinity masks either, but #85168 might get the ball rolling on that.

[RKSimon]

Use ADLPPort04_09 instead - adding the other ProcResGroup combos to X86SchedAlderlakeP.td shouldn't be a problem.

[boomanaiden154]

Can't believe I missed that one along with 1-2 others. I've added in the ones that were missing as well to X86SchedAlderlakeP.td, along with a ADLPPortAny ProcResGroup so that all of the overlapping groups have a super group (I believe that won't cause any issues?).

[RKSimon]

Setting an CPU affinity mask was what I had in mind

[RKSimon]

LGTM