[X86] Fix instr desc of CFCMOV's 'mr' variants

[darkbuck]

• With the memory operand as the destination, 'mr' variants of CFCMOV
  works like STORE and their memory operands should be input operands
  instead of output ones.

[llvmbot]

@llvm/pr-subscribers-backend-x86

Author: None (darkbuck)

Changes

• With the memory operand as the destination, 'mr' variants of CFCMOV
  works like STORE and their memory operands should be input operands
  instead of output ones.

---

Full diff: https://github.com/llvm/llvm-project/pull/88970.diff

1 Files Affected:

• (modified) llvm/lib/Target/X86/X86InstrCMovSetCC.td (+2-2)

diff --git a/llvm/lib/Target/X86/X86InstrCMovSetCC.td b/llvm/lib/Target/X86/X86InstrCMovSetCC.td
index 27a0c889a4da3e..e27aa4115990e9 100644
--- a/llvm/lib/Target/X86/X86InstrCMovSetCC.td
+++ b/llvm/lib/Target/X86/X86InstrCMovSetCC.td
@@ -58,8 +58,8 @@ let SchedRW = [WriteCMOV.Folded, WriteCMOV.ReadAfterFold] in {
 }
 let SchedRW = [WriteCMOV, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault],
     Predicates = [HasCMOV, HasCF, In64BitMode], mayStore = 1 in
-  def mr : ITy<0x40, MRMDestMemCC, t, (outs t.MemOperand:$dst),
-                (ins t.RegClass:$src1, ccode:$cond),
+  def mr : ITy<0x40, MRMDestMemCC, t, (outs),
+                (ins t.MemOperand:$dst, t.RegClass:$src1, ccode:$cond),
                 "cfcmov${cond}", unaryop_ndd_args, []>, UseEFLAGS, NF;
 }
 

[darkbuck]

This fix is separated from the original one so that the original change to TableGen is clean.

[KanRobert]

LGTM