RenameIndependentSubregs: Add missing sub-range for new IMPLICIT_DEFs #89050
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@llvm/pr-subscribers-backend-amdgpu @llvm/pr-subscribers-llvm-regalloc Author: Petar Avramovic (petar-avramovic) ChangesExisting sub-ranges are correctly updated because new IMPLICIT_DEF is Patch is 27.83 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/89050.diff 2 Files Affected:
diff --git a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
index bc3ef1c0329a98..e888f290df510d 100644
--- a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
+++ b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
@@ -334,10 +334,17 @@ void RenameIndependentSubregs::computeMainRangesFixFlags(
DebugLoc(), MCDesc, Reg);
SlotIndex DefIdx = LIS->InsertMachineInstrInMaps(*ImpDef);
SlotIndex RegDefIdx = DefIdx.getRegSlot();
+ LaneBitmask Mask = MRI->getMaxLaneMaskForVReg(Reg);
for (LiveInterval::SubRange &SR : LI.subranges()) {
+ Mask = Mask & ~SR.LaneMask;
VNInfo *SRVNI = SR.getNextValue(RegDefIdx, Allocator);
SR.addSegment(LiveRange::Segment(RegDefIdx, PredEnd, SRVNI));
}
+
+ if (!Mask.none()) {
+ LiveInterval::SubRange *SR = LI.createSubRange(Allocator, Mask);
+ SR->createDeadDef(RegDefIdx, Allocator);
+ }
}
}
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
index 47e476de74cf41..6e96a4ddbc0b3b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
@@ -144,40 +144,42 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16(i64 %node_ptr, float
define amdgpu_ps <4 x float> @image_bvh_intersect_ray_vgpr_descr(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr) {
; GFX1030-LABEL: image_bvh_intersect_ray_vgpr_descr:
; GFX1030: ; %bb.0:
-; GFX1030-NEXT: v_mov_b32_e32 v15, v0
-; GFX1030-NEXT: v_mov_b32_e32 v16, v1
-; GFX1030-NEXT: v_mov_b32_e32 v17, v2
-; GFX1030-NEXT: v_mov_b32_e32 v18, v3
-; GFX1030-NEXT: v_mov_b32_e32 v19, v4
-; GFX1030-NEXT: v_mov_b32_e32 v20, v5
-; GFX1030-NEXT: v_mov_b32_e32 v21, v6
-; GFX1030-NEXT: v_mov_b32_e32 v22, v7
-; GFX1030-NEXT: v_mov_b32_e32 v23, v8
-; GFX1030-NEXT: v_mov_b32_e32 v24, v9
-; GFX1030-NEXT: v_mov_b32_e32 v25, v10
+; GFX1030-NEXT: v_mov_b32_e32 v21, v0
+; GFX1030-NEXT: v_mov_b32_e32 v22, v1
+; GFX1030-NEXT: v_mov_b32_e32 v23, v2
+; GFX1030-NEXT: v_mov_b32_e32 v24, v3
+; GFX1030-NEXT: v_mov_b32_e32 v25, v4
+; GFX1030-NEXT: v_mov_b32_e32 v26, v5
+; GFX1030-NEXT: v_mov_b32_e32 v27, v6
+; GFX1030-NEXT: v_mov_b32_e32 v28, v7
+; GFX1030-NEXT: v_mov_b32_e32 v29, v8
+; GFX1030-NEXT: v_mov_b32_e32 v30, v9
+; GFX1030-NEXT: v_mov_b32_e32 v31, v10
+; GFX1030-NEXT: v_mov_b32_e32 v19, v11
+; GFX1030-NEXT: v_mov_b32_e32 v20, v12
; GFX1030-NEXT: s_mov_b32 s1, exec_lo
; GFX1030-NEXT: .LBB6_1: ; =>This Inner Loop Header: Depth=1
-; GFX1030-NEXT: v_readfirstlane_b32 s4, v11
-; GFX1030-NEXT: v_readfirstlane_b32 s5, v12
+; GFX1030-NEXT: v_readfirstlane_b32 s4, v19
+; GFX1030-NEXT: v_readfirstlane_b32 s5, v20
; GFX1030-NEXT: v_readfirstlane_b32 s6, v13
; GFX1030-NEXT: v_readfirstlane_b32 s7, v14
-; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[11:12]
+; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[19:20]
; GFX1030-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[13:14]
; GFX1030-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX1030-NEXT: s_and_saveexec_b32 s0, s0
-; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[15:25], s[4:7]
-; GFX1030-NEXT: ; implicit-def: $vgpr11
-; GFX1030-NEXT: ; implicit-def: $vgpr15
-; GFX1030-NEXT: ; implicit-def: $vgpr16
-; GFX1030-NEXT: ; implicit-def: $vgpr17
-; GFX1030-NEXT: ; implicit-def: $vgpr18
+; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[21:31], s[4:7]
; GFX1030-NEXT: ; implicit-def: $vgpr19
-; GFX1030-NEXT: ; implicit-def: $vgpr20
; GFX1030-NEXT: ; implicit-def: $vgpr21
; GFX1030-NEXT: ; implicit-def: $vgpr22
; GFX1030-NEXT: ; implicit-def: $vgpr23
; GFX1030-NEXT: ; implicit-def: $vgpr24
; GFX1030-NEXT: ; implicit-def: $vgpr25
+; GFX1030-NEXT: ; implicit-def: $vgpr26
+; GFX1030-NEXT: ; implicit-def: $vgpr27
+; GFX1030-NEXT: ; implicit-def: $vgpr28
+; GFX1030-NEXT: ; implicit-def: $vgpr29
+; GFX1030-NEXT: ; implicit-def: $vgpr30
+; GFX1030-NEXT: ; implicit-def: $vgpr31
; GFX1030-NEXT: ; implicit-def: $vgpr11_vgpr12_vgpr13_vgpr14
; GFX1030-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1030-NEXT: s_cbranch_execnz .LBB6_1
@@ -188,18 +190,20 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_vgpr_descr(i32 %node_ptr,
;
; GFX1013-LABEL: image_bvh_intersect_ray_vgpr_descr:
; GFX1013: ; %bb.0:
+; GFX1013-NEXT: v_mov_b32_e32 v19, v11
+; GFX1013-NEXT: v_mov_b32_e32 v20, v12
; GFX1013-NEXT: s_mov_b32 s1, exec_lo
; GFX1013-NEXT: .LBB6_1: ; =>This Inner Loop Header: Depth=1
-; GFX1013-NEXT: v_readfirstlane_b32 s4, v11
-; GFX1013-NEXT: v_readfirstlane_b32 s5, v12
+; GFX1013-NEXT: v_readfirstlane_b32 s4, v19
+; GFX1013-NEXT: v_readfirstlane_b32 s5, v20
; GFX1013-NEXT: v_readfirstlane_b32 s6, v13
; GFX1013-NEXT: v_readfirstlane_b32 s7, v14
-; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[11:12]
+; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[19:20]
; GFX1013-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[13:14]
; GFX1013-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX1013-NEXT: s_and_saveexec_b32 s0, s0
; GFX1013-NEXT: image_bvh_intersect_ray v[15:18], v[0:10], s[4:7]
-; GFX1013-NEXT: ; implicit-def: $vgpr11
+; GFX1013-NEXT: ; implicit-def: $vgpr19
; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10
; GFX1013-NEXT: ; implicit-def: $vgpr11_vgpr12_vgpr13_vgpr14
; GFX1013-NEXT: s_waitcnt_depctr 0xffe3
@@ -216,25 +220,27 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_vgpr_descr(i32 %node_ptr,
;
; GFX11-LABEL: image_bvh_intersect_ray_vgpr_descr:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_dual_mov_b32 v18, v0 :: v_dual_mov_b32 v19, v1
+; GFX11-NEXT: v_dual_mov_b32 v20, v0 :: v_dual_mov_b32 v21, v1
; GFX11-NEXT: v_dual_mov_b32 v15, v2 :: v_dual_mov_b32 v16, v3
-; GFX11-NEXT: v_mov_b32_e32 v17, v4
+; GFX11-NEXT: v_dual_mov_b32 v17, v4 :: v_dual_mov_b32 v18, v11
+; GFX11-NEXT: v_mov_b32_e32 v19, v12
; GFX11-NEXT: s_mov_b32 s1, exec_lo
; GFX11-NEXT: .LBB6_1: ; =>This Inner Loop Header: Depth=1
-; GFX11-NEXT: v_readfirstlane_b32 s4, v11
-; GFX11-NEXT: v_readfirstlane_b32 s5, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_readfirstlane_b32 s4, v18
+; GFX11-NEXT: v_readfirstlane_b32 s5, v19
; GFX11-NEXT: v_readfirstlane_b32 s6, v13
; GFX11-NEXT: v_readfirstlane_b32 s7, v14
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[11:12]
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[18:19]
; GFX11-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[13:14]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX11-NEXT: s_and_saveexec_b32 s0, s0
-; GFX11-NEXT: image_bvh_intersect_ray v[0:3], [v18, v19, v[15:17], v[5:7], v[8:10]], s[4:7]
-; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: image_bvh_intersect_ray v[0:3], [v20, v21, v[15:17], v[5:7], v[8:10]], s[4:7]
; GFX11-NEXT: ; implicit-def: $vgpr18
-; GFX11-NEXT: ; implicit-def: $vgpr19
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr21
; GFX11-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17
; GFX11-NEXT: ; implicit-def: $vgpr5_vgpr6_vgpr7
; GFX11-NEXT: ; implicit-def: $vgpr8_vgpr9_vgpr10
@@ -253,39 +259,41 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_vgpr_descr(i32 %node_ptr,
define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16_vgpr_descr(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr) {
; GFX1030-LABEL: image_bvh_intersect_ray_a16_vgpr_descr:
; GFX1030: ; %bb.0:
-; GFX1030-NEXT: v_mov_b32_e32 v13, v0
-; GFX1030-NEXT: v_mov_b32_e32 v14, v1
+; GFX1030-NEXT: v_mov_b32_e32 v18, v0
+; GFX1030-NEXT: v_mov_b32_e32 v19, v1
; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 16, v5
; GFX1030-NEXT: v_and_b32_e32 v1, 0xffff, v7
-; GFX1030-NEXT: v_mov_b32_e32 v15, v2
+; GFX1030-NEXT: v_mov_b32_e32 v20, v2
; GFX1030-NEXT: v_and_b32_e32 v2, 0xffff, v8
-; GFX1030-NEXT: v_mov_b32_e32 v16, v3
+; GFX1030-NEXT: v_mov_b32_e32 v21, v3
; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX1030-NEXT: v_mov_b32_e32 v17, v4
-; GFX1030-NEXT: v_alignbit_b32 v20, v2, v7, 16
+; GFX1030-NEXT: v_mov_b32_e32 v22, v4
+; GFX1030-NEXT: v_mov_b32_e32 v16, v9
+; GFX1030-NEXT: v_mov_b32_e32 v17, v10
+; GFX1030-NEXT: v_and_or_b32 v23, 0xffff, v5, v0
+; GFX1030-NEXT: v_and_or_b32 v24, 0xffff, v6, v1
+; GFX1030-NEXT: v_alignbit_b32 v25, v2, v7, 16
; GFX1030-NEXT: s_mov_b32 s1, exec_lo
-; GFX1030-NEXT: v_and_or_b32 v18, 0xffff, v5, v0
-; GFX1030-NEXT: v_and_or_b32 v19, 0xffff, v6, v1
; GFX1030-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1
-; GFX1030-NEXT: v_readfirstlane_b32 s4, v9
-; GFX1030-NEXT: v_readfirstlane_b32 s5, v10
+; GFX1030-NEXT: v_readfirstlane_b32 s4, v16
+; GFX1030-NEXT: v_readfirstlane_b32 s5, v17
; GFX1030-NEXT: v_readfirstlane_b32 s6, v11
; GFX1030-NEXT: v_readfirstlane_b32 s7, v12
-; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[9:10]
+; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[16:17]
; GFX1030-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[11:12]
; GFX1030-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX1030-NEXT: s_and_saveexec_b32 s0, s0
-; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[13:20], s[4:7] a16
-; GFX1030-NEXT: ; implicit-def: $vgpr9
-; GFX1030-NEXT: ; implicit-def: $vgpr13
-; GFX1030-NEXT: ; implicit-def: $vgpr14
-; GFX1030-NEXT: ; implicit-def: $vgpr15
+; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[18:25], s[4:7] a16
; GFX1030-NEXT: ; implicit-def: $vgpr16
-; GFX1030-NEXT: ; implicit-def: $vgpr17
; GFX1030-NEXT: ; implicit-def: $vgpr18
; GFX1030-NEXT: ; implicit-def: $vgpr19
; GFX1030-NEXT: ; implicit-def: $vgpr20
+; GFX1030-NEXT: ; implicit-def: $vgpr21
+; GFX1030-NEXT: ; implicit-def: $vgpr22
+; GFX1030-NEXT: ; implicit-def: $vgpr23
+; GFX1030-NEXT: ; implicit-def: $vgpr24
+; GFX1030-NEXT: ; implicit-def: $vgpr25
; GFX1030-NEXT: ; implicit-def: $vgpr9_vgpr10_vgpr11_vgpr12
; GFX1030-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1030-NEXT: s_cbranch_execnz .LBB7_1
@@ -296,26 +304,28 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16_vgpr_descr(i32 %node_p
;
; GFX1013-LABEL: image_bvh_intersect_ray_a16_vgpr_descr:
; GFX1013: ; %bb.0:
-; GFX1013-NEXT: v_lshrrev_b32_e32 v13, 16, v5
-; GFX1013-NEXT: v_and_b32_e32 v14, 0xffff, v7
+; GFX1013-NEXT: v_mov_b32_e32 v17, v9
+; GFX1013-NEXT: v_mov_b32_e32 v18, v10
+; GFX1013-NEXT: v_lshrrev_b32_e32 v9, 16, v5
+; GFX1013-NEXT: v_and_b32_e32 v10, 0xffff, v7
; GFX1013-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX1013-NEXT: s_mov_b32 s1, exec_lo
-; GFX1013-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX1013-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX1013-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX1013-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX1013-NEXT: v_alignbit_b32 v7, v8, v7, 16
-; GFX1013-NEXT: v_and_or_b32 v5, 0xffff, v5, v13
-; GFX1013-NEXT: v_and_or_b32 v6, 0xffff, v6, v14
+; GFX1013-NEXT: v_and_or_b32 v5, 0xffff, v5, v9
+; GFX1013-NEXT: v_and_or_b32 v6, 0xffff, v6, v10
; GFX1013-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1
-; GFX1013-NEXT: v_readfirstlane_b32 s4, v9
-; GFX1013-NEXT: v_readfirstlane_b32 s5, v10
+; GFX1013-NEXT: v_readfirstlane_b32 s4, v17
+; GFX1013-NEXT: v_readfirstlane_b32 s5, v18
; GFX1013-NEXT: v_readfirstlane_b32 s6, v11
; GFX1013-NEXT: v_readfirstlane_b32 s7, v12
-; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[9:10]
+; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[17:18]
; GFX1013-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[11:12]
; GFX1013-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX1013-NEXT: s_and_saveexec_b32 s0, s0
; GFX1013-NEXT: image_bvh_intersect_ray v[13:16], v[0:7], s[4:7] a16
-; GFX1013-NEXT: ; implicit-def: $vgpr9
+; GFX1013-NEXT: ; implicit-def: $vgpr17
; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX1013-NEXT: ; implicit-def: $vgpr9_vgpr10_vgpr11_vgpr12
; GFX1013-NEXT: s_waitcnt_depctr 0xffe3
@@ -333,27 +343,28 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16_vgpr_descr(i32 %node_p
; GFX11-LABEL: image_bvh_intersect_ray_a16_vgpr_descr:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_dual_mov_b32 v16, v0 :: v_dual_mov_b32 v17, v1
-; GFX11-NEXT: v_dual_mov_b32 v15, v4 :: v_dual_and_b32 v0, 0xffff, v7
+; GFX11-NEXT: v_dual_mov_b32 v19, v10 :: v_dual_and_b32 v0, 0xffff, v7
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v8
; GFX11-NEXT: v_dual_mov_b32 v13, v2 :: v_dual_mov_b32 v14, v3
-; GFX11-NEXT: s_mov_b32 s1, exec_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_dual_mov_b32 v15, v4 :: v_dual_mov_b32 v18, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_lshl_or_b32 v4, v5, 16, v0
; GFX11-NEXT: v_perm_b32 v5, v5, v7, 0x7060302
; GFX11-NEXT: v_lshl_or_b32 v6, v6, 16, v1
+; GFX11-NEXT: s_mov_b32 s1, exec_lo
; GFX11-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1
-; GFX11-NEXT: v_readfirstlane_b32 s4, v9
-; GFX11-NEXT: v_readfirstlane_b32 s5, v10
+; GFX11-NEXT: v_readfirstlane_b32 s4, v18
+; GFX11-NEXT: v_readfirstlane_b32 s5, v19
; GFX11-NEXT: v_readfirstlane_b32 s6, v11
; GFX11-NEXT: v_readfirstlane_b32 s7, v12
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[9:10]
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[18:19]
; GFX11-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[11:12]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX11-NEXT: s_and_saveexec_b32 s0, s0
; GFX11-NEXT: image_bvh_intersect_ray v[0:3], [v16, v17, v[13:15], v[4:6]], s[4:7] a16
-; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: ; implicit-def: $vgpr16
; GFX11-NEXT: ; implicit-def: $vgpr17
; GFX11-NEXT: ; implicit-def: $vgpr13_vgpr14_vgpr15
@@ -373,42 +384,44 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16_vgpr_descr(i32 %node_p
define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_vgpr_descr(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr) {
; GFX1030-LABEL: image_bvh64_intersect_ray_vgpr_descr:
; GFX1030: ; %bb.0:
-; GFX1030-NEXT: v_mov_b32_e32 v16, v0
-; GFX1030-NEXT: v_mov_b32_e32 v17, v1
-; GFX1030-NEXT: v_mov_b32_e32 v18, v2
-; GFX1030-NEXT: v_mov_b32_e32 v19, v3
-; GFX1030-NEXT: v_mov_b32_e32 v20, v4
-; GFX1030-NEXT: v_mov_b32_e32 v21, v5
-; GFX1030-NEXT: v_mov_b32_e32 v22, v6
-; GFX1030-NEXT: v_mov_b32_e32 v23, v7
-; GFX1030-NEXT: v_mov_b32_e32 v24, v8
-; GFX1030-NEXT: v_mov_b32_e32 v25, v9
-; GFX1030-NEXT: v_mov_b32_e32 v26, v10
-; GFX1030-NEXT: v_mov_b32_e32 v27, v11
+; GFX1030-NEXT: v_mov_b32_e32 v22, v0
+; GFX1030-NEXT: v_mov_b32_e32 v23, v1
+; GFX1030-NEXT: v_mov_b32_e32 v24, v2
+; GFX1030-NEXT: v_mov_b32_e32 v25, v3
+; GFX1030-NEXT: v_mov_b32_e32 v26, v4
+; GFX1030-NEXT: v_mov_b32_e32 v27, v5
+; GFX1030-NEXT: v_mov_b32_e32 v28, v6
+; GFX1030-NEXT: v_mov_b32_e32 v29, v7
+; GFX1030-NEXT: v_mov_b32_e32 v30, v8
+; GFX1030-NEXT: v_mov_b32_e32 v31, v9
+; GFX1030-NEXT: v_mov_b32_e32 v32, v10
+; GFX1030-NEXT: v_mov_b32_e32 v33, v11
+; GFX1030-NEXT: v_mov_b32_e32 v20, v12
+; GFX1030-NEXT: v_mov_b32_e32 v21, v13
; GFX1030-NEXT: s_mov_b32 s1, exec_lo
; GFX1030-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
-; GFX1030-NEXT: v_readfirstlane_b32 s4, v12
-; GFX1030-NEXT: v_readfirstlane_b32 s5, v13
+; GFX1030-NEXT: v_readfirstlane_b32 s4, v20
+; GFX1030-NEXT: v_readfirstlane_b32 s5, v21
; GFX1030-NEXT: v_readfirstlane_b32 s6, v14
; GFX1030-NEXT: v_readfirstlane_b32 s7, v15
-; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[12:13]
+; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[20:21]
; GFX1030-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[14:15]
; GFX1030-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX1030-NEXT: s_and_saveexec_b32 s0, s0
-; GFX1030-NEXT: image_bvh64_intersect_ray v[0:3], v[16:27], s[4:7]
-; GFX1030-NEXT: ; implicit-def: $vgpr12
-; GFX1030-NEXT: ; implicit-def: $vgpr16
-; GFX1030-NEXT: ; implicit-def: $vgpr17
-; GFX1030-NEXT: ; implicit-def: $vgpr18
-; GFX1030-NEXT: ; implicit-def: $vgpr19
+; GFX1030-NEXT: image_bvh64_intersect_ray v[0:3], v[22:33], s[4:7]
; GFX1030-NEXT: ; implicit-def: $vgpr20
-; GFX1030-NEXT: ; implicit-def: $vgpr21
; GFX1030-NEXT: ; implicit-def: $vgpr22
; GFX1030-NEXT: ; implicit-def: $vgpr23
; GFX1030-NEXT: ; implicit-def: $vgpr24
; GFX1030-NEXT: ; implicit-def: $vgpr25
; GFX1030-NEXT: ; implicit-def: $vgpr26
; GFX1030-NEXT: ; implicit-def: $vgpr27
+; GFX1030-NEXT: ; implicit-def: $vgpr28
+; GFX1030-NEXT: ; implicit-def: $vgpr29
+; GFX1030-NEXT: ; implicit-def: $vgpr30
+; GFX1030-NEXT: ; implicit-def: $vgpr31
+; GFX1030-NEXT: ; implicit-def: $vgpr32
+; GFX1030-NEXT: ; implicit-def: $vgpr33
; GFX1030-NEXT: ; implicit-def: $vgpr12_vgpr13_vgpr14_vgpr15
; GFX1030-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1030-NEXT: s_cbranch_execnz .LBB8_1
@@ -419,18 +432,20 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_vgpr_descr(i64 %node_ptr
;
; GFX1013-LABEL: image_bvh64_intersect_ray_vgpr_descr:
; GFX1013: ; %bb.0:
+; GFX1013-NEXT: v_mov_b32_e32 v20, v12
+; GFX1013-NEXT: v_mov_b32_e32 v21, v13
; GFX1013-NEXT: s_mov_b32 s1, exec_lo
; GFX1013-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
-; GFX1013-NEXT: v_readfirstlane_b32 s4, v12
-; GFX1013-NEXT: v_readfirstlane_b32 s5, v13
+; GFX1013-NEXT: v_readfirstlane_b32 s4, v20
+; GFX1013-NEXT: v_readfirstlane_b32 s5, v21
; GFX1013-NEXT: v_readfirstlane_b32 s6, v14
; GFX1013-NEXT: v_readfirstlane_b32 s7, v15
-; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[12:13]
+; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[20:21]
; GFX1013-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[14:15]
; GFX1013-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX1013-NEXT: s_and_saveexec_b32 s0, s0
; GFX1013-NEXT: image_bvh64_intersect_ray v[16:19], v[0:11], s[4:7]
-; GFX1013-NEXT: ; implicit-def: $vgpr12
+; GFX1013-NEXT: ; implicit-def: $vgpr20
; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11
; GFX1013-NEXT: ; implicit-def: $vgpr12_vgpr13_vgpr14_vgpr15
; GFX1013-NEXT: s_waitcnt_depctr 0xffe3
@@ -450,20 +465,22 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_vgpr_descr(i64 %node_ptr
; GFX11-NEXT: v_dual_mov_b32 v19, v0 :: v_dual_mov_b32 v20, v1
; GFX11-NEXT: v_dual_mov_b32 v21, v2 :: v_dual_mov_b32 v16, v3
; GFX11-NEXT: v_dual_mov_b32 v17, v4 :: v_dual_mov_b32 v18, v5
+; GFX11-NEXT: v_dual_mov_b32 v4, v12 :: v_dual_mov_b32 v5, v13
; GFX11-NEXT: s_mov_b32 s1, exec_lo
; GFX11-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
-; GFX11-NEXT: v_readfirstlane_b32 s4, v12
-; GFX11-NEXT: v_readfirstlane_b32 s5, v13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_readfirstlane_b32 s4, v4
+; GFX11-NEXT: v_readfirstlane_b32 s5, v5
; GFX11-NEXT: v_readfirstlane_b32 s6, v14
; GFX11-NEXT: v_readfirstlane_b32 s7, v15
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[12:13]
+;...
[truncated]
|
|
@llvm/pr-subscribers-llvm-globalisel Author: Petar Avramovic (petar-avramovic) ChangesExisting sub-ranges are correctly updated because new IMPLICIT_DEF is Patch is 27.83 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/89050.diff 2 Files Affected:
diff --git a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
index bc3ef1c0329a98..e888f290df510d 100644
--- a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
+++ b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
@@ -334,10 +334,17 @@ void RenameIndependentSubregs::computeMainRangesFixFlags(
DebugLoc(), MCDesc, Reg);
SlotIndex DefIdx = LIS->InsertMachineInstrInMaps(*ImpDef);
SlotIndex RegDefIdx = DefIdx.getRegSlot();
+ LaneBitmask Mask = MRI->getMaxLaneMaskForVReg(Reg);
for (LiveInterval::SubRange &SR : LI.subranges()) {
+ Mask = Mask & ~SR.LaneMask;
VNInfo *SRVNI = SR.getNextValue(RegDefIdx, Allocator);
SR.addSegment(LiveRange::Segment(RegDefIdx, PredEnd, SRVNI));
}
+
+ if (!Mask.none()) {
+ LiveInterval::SubRange *SR = LI.createSubRange(Allocator, Mask);
+ SR->createDeadDef(RegDefIdx, Allocator);
+ }
}
}
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
index 47e476de74cf41..6e96a4ddbc0b3b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
@@ -144,40 +144,42 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16(i64 %node_ptr, float
define amdgpu_ps <4 x float> @image_bvh_intersect_ray_vgpr_descr(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr) {
; GFX1030-LABEL: image_bvh_intersect_ray_vgpr_descr:
; GFX1030: ; %bb.0:
-; GFX1030-NEXT: v_mov_b32_e32 v15, v0
-; GFX1030-NEXT: v_mov_b32_e32 v16, v1
-; GFX1030-NEXT: v_mov_b32_e32 v17, v2
-; GFX1030-NEXT: v_mov_b32_e32 v18, v3
-; GFX1030-NEXT: v_mov_b32_e32 v19, v4
-; GFX1030-NEXT: v_mov_b32_e32 v20, v5
-; GFX1030-NEXT: v_mov_b32_e32 v21, v6
-; GFX1030-NEXT: v_mov_b32_e32 v22, v7
-; GFX1030-NEXT: v_mov_b32_e32 v23, v8
-; GFX1030-NEXT: v_mov_b32_e32 v24, v9
-; GFX1030-NEXT: v_mov_b32_e32 v25, v10
+; GFX1030-NEXT: v_mov_b32_e32 v21, v0
+; GFX1030-NEXT: v_mov_b32_e32 v22, v1
+; GFX1030-NEXT: v_mov_b32_e32 v23, v2
+; GFX1030-NEXT: v_mov_b32_e32 v24, v3
+; GFX1030-NEXT: v_mov_b32_e32 v25, v4
+; GFX1030-NEXT: v_mov_b32_e32 v26, v5
+; GFX1030-NEXT: v_mov_b32_e32 v27, v6
+; GFX1030-NEXT: v_mov_b32_e32 v28, v7
+; GFX1030-NEXT: v_mov_b32_e32 v29, v8
+; GFX1030-NEXT: v_mov_b32_e32 v30, v9
+; GFX1030-NEXT: v_mov_b32_e32 v31, v10
+; GFX1030-NEXT: v_mov_b32_e32 v19, v11
+; GFX1030-NEXT: v_mov_b32_e32 v20, v12
; GFX1030-NEXT: s_mov_b32 s1, exec_lo
; GFX1030-NEXT: .LBB6_1: ; =>This Inner Loop Header: Depth=1
-; GFX1030-NEXT: v_readfirstlane_b32 s4, v11
-; GFX1030-NEXT: v_readfirstlane_b32 s5, v12
+; GFX1030-NEXT: v_readfirstlane_b32 s4, v19
+; GFX1030-NEXT: v_readfirstlane_b32 s5, v20
; GFX1030-NEXT: v_readfirstlane_b32 s6, v13
; GFX1030-NEXT: v_readfirstlane_b32 s7, v14
-; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[11:12]
+; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[19:20]
; GFX1030-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[13:14]
; GFX1030-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX1030-NEXT: s_and_saveexec_b32 s0, s0
-; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[15:25], s[4:7]
-; GFX1030-NEXT: ; implicit-def: $vgpr11
-; GFX1030-NEXT: ; implicit-def: $vgpr15
-; GFX1030-NEXT: ; implicit-def: $vgpr16
-; GFX1030-NEXT: ; implicit-def: $vgpr17
-; GFX1030-NEXT: ; implicit-def: $vgpr18
+; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[21:31], s[4:7]
; GFX1030-NEXT: ; implicit-def: $vgpr19
-; GFX1030-NEXT: ; implicit-def: $vgpr20
; GFX1030-NEXT: ; implicit-def: $vgpr21
; GFX1030-NEXT: ; implicit-def: $vgpr22
; GFX1030-NEXT: ; implicit-def: $vgpr23
; GFX1030-NEXT: ; implicit-def: $vgpr24
; GFX1030-NEXT: ; implicit-def: $vgpr25
+; GFX1030-NEXT: ; implicit-def: $vgpr26
+; GFX1030-NEXT: ; implicit-def: $vgpr27
+; GFX1030-NEXT: ; implicit-def: $vgpr28
+; GFX1030-NEXT: ; implicit-def: $vgpr29
+; GFX1030-NEXT: ; implicit-def: $vgpr30
+; GFX1030-NEXT: ; implicit-def: $vgpr31
; GFX1030-NEXT: ; implicit-def: $vgpr11_vgpr12_vgpr13_vgpr14
; GFX1030-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1030-NEXT: s_cbranch_execnz .LBB6_1
@@ -188,18 +190,20 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_vgpr_descr(i32 %node_ptr,
;
; GFX1013-LABEL: image_bvh_intersect_ray_vgpr_descr:
; GFX1013: ; %bb.0:
+; GFX1013-NEXT: v_mov_b32_e32 v19, v11
+; GFX1013-NEXT: v_mov_b32_e32 v20, v12
; GFX1013-NEXT: s_mov_b32 s1, exec_lo
; GFX1013-NEXT: .LBB6_1: ; =>This Inner Loop Header: Depth=1
-; GFX1013-NEXT: v_readfirstlane_b32 s4, v11
-; GFX1013-NEXT: v_readfirstlane_b32 s5, v12
+; GFX1013-NEXT: v_readfirstlane_b32 s4, v19
+; GFX1013-NEXT: v_readfirstlane_b32 s5, v20
; GFX1013-NEXT: v_readfirstlane_b32 s6, v13
; GFX1013-NEXT: v_readfirstlane_b32 s7, v14
-; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[11:12]
+; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[19:20]
; GFX1013-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[13:14]
; GFX1013-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX1013-NEXT: s_and_saveexec_b32 s0, s0
; GFX1013-NEXT: image_bvh_intersect_ray v[15:18], v[0:10], s[4:7]
-; GFX1013-NEXT: ; implicit-def: $vgpr11
+; GFX1013-NEXT: ; implicit-def: $vgpr19
; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10
; GFX1013-NEXT: ; implicit-def: $vgpr11_vgpr12_vgpr13_vgpr14
; GFX1013-NEXT: s_waitcnt_depctr 0xffe3
@@ -216,25 +220,27 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_vgpr_descr(i32 %node_ptr,
;
; GFX11-LABEL: image_bvh_intersect_ray_vgpr_descr:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_dual_mov_b32 v18, v0 :: v_dual_mov_b32 v19, v1
+; GFX11-NEXT: v_dual_mov_b32 v20, v0 :: v_dual_mov_b32 v21, v1
; GFX11-NEXT: v_dual_mov_b32 v15, v2 :: v_dual_mov_b32 v16, v3
-; GFX11-NEXT: v_mov_b32_e32 v17, v4
+; GFX11-NEXT: v_dual_mov_b32 v17, v4 :: v_dual_mov_b32 v18, v11
+; GFX11-NEXT: v_mov_b32_e32 v19, v12
; GFX11-NEXT: s_mov_b32 s1, exec_lo
; GFX11-NEXT: .LBB6_1: ; =>This Inner Loop Header: Depth=1
-; GFX11-NEXT: v_readfirstlane_b32 s4, v11
-; GFX11-NEXT: v_readfirstlane_b32 s5, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_readfirstlane_b32 s4, v18
+; GFX11-NEXT: v_readfirstlane_b32 s5, v19
; GFX11-NEXT: v_readfirstlane_b32 s6, v13
; GFX11-NEXT: v_readfirstlane_b32 s7, v14
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[11:12]
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[18:19]
; GFX11-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[13:14]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX11-NEXT: s_and_saveexec_b32 s0, s0
-; GFX11-NEXT: image_bvh_intersect_ray v[0:3], [v18, v19, v[15:17], v[5:7], v[8:10]], s[4:7]
-; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: image_bvh_intersect_ray v[0:3], [v20, v21, v[15:17], v[5:7], v[8:10]], s[4:7]
; GFX11-NEXT: ; implicit-def: $vgpr18
-; GFX11-NEXT: ; implicit-def: $vgpr19
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr21
; GFX11-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17
; GFX11-NEXT: ; implicit-def: $vgpr5_vgpr6_vgpr7
; GFX11-NEXT: ; implicit-def: $vgpr8_vgpr9_vgpr10
@@ -253,39 +259,41 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_vgpr_descr(i32 %node_ptr,
define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16_vgpr_descr(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr) {
; GFX1030-LABEL: image_bvh_intersect_ray_a16_vgpr_descr:
; GFX1030: ; %bb.0:
-; GFX1030-NEXT: v_mov_b32_e32 v13, v0
-; GFX1030-NEXT: v_mov_b32_e32 v14, v1
+; GFX1030-NEXT: v_mov_b32_e32 v18, v0
+; GFX1030-NEXT: v_mov_b32_e32 v19, v1
; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 16, v5
; GFX1030-NEXT: v_and_b32_e32 v1, 0xffff, v7
-; GFX1030-NEXT: v_mov_b32_e32 v15, v2
+; GFX1030-NEXT: v_mov_b32_e32 v20, v2
; GFX1030-NEXT: v_and_b32_e32 v2, 0xffff, v8
-; GFX1030-NEXT: v_mov_b32_e32 v16, v3
+; GFX1030-NEXT: v_mov_b32_e32 v21, v3
; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX1030-NEXT: v_mov_b32_e32 v17, v4
-; GFX1030-NEXT: v_alignbit_b32 v20, v2, v7, 16
+; GFX1030-NEXT: v_mov_b32_e32 v22, v4
+; GFX1030-NEXT: v_mov_b32_e32 v16, v9
+; GFX1030-NEXT: v_mov_b32_e32 v17, v10
+; GFX1030-NEXT: v_and_or_b32 v23, 0xffff, v5, v0
+; GFX1030-NEXT: v_and_or_b32 v24, 0xffff, v6, v1
+; GFX1030-NEXT: v_alignbit_b32 v25, v2, v7, 16
; GFX1030-NEXT: s_mov_b32 s1, exec_lo
-; GFX1030-NEXT: v_and_or_b32 v18, 0xffff, v5, v0
-; GFX1030-NEXT: v_and_or_b32 v19, 0xffff, v6, v1
; GFX1030-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1
-; GFX1030-NEXT: v_readfirstlane_b32 s4, v9
-; GFX1030-NEXT: v_readfirstlane_b32 s5, v10
+; GFX1030-NEXT: v_readfirstlane_b32 s4, v16
+; GFX1030-NEXT: v_readfirstlane_b32 s5, v17
; GFX1030-NEXT: v_readfirstlane_b32 s6, v11
; GFX1030-NEXT: v_readfirstlane_b32 s7, v12
-; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[9:10]
+; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[16:17]
; GFX1030-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[11:12]
; GFX1030-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX1030-NEXT: s_and_saveexec_b32 s0, s0
-; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[13:20], s[4:7] a16
-; GFX1030-NEXT: ; implicit-def: $vgpr9
-; GFX1030-NEXT: ; implicit-def: $vgpr13
-; GFX1030-NEXT: ; implicit-def: $vgpr14
-; GFX1030-NEXT: ; implicit-def: $vgpr15
+; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[18:25], s[4:7] a16
; GFX1030-NEXT: ; implicit-def: $vgpr16
-; GFX1030-NEXT: ; implicit-def: $vgpr17
; GFX1030-NEXT: ; implicit-def: $vgpr18
; GFX1030-NEXT: ; implicit-def: $vgpr19
; GFX1030-NEXT: ; implicit-def: $vgpr20
+; GFX1030-NEXT: ; implicit-def: $vgpr21
+; GFX1030-NEXT: ; implicit-def: $vgpr22
+; GFX1030-NEXT: ; implicit-def: $vgpr23
+; GFX1030-NEXT: ; implicit-def: $vgpr24
+; GFX1030-NEXT: ; implicit-def: $vgpr25
; GFX1030-NEXT: ; implicit-def: $vgpr9_vgpr10_vgpr11_vgpr12
; GFX1030-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1030-NEXT: s_cbranch_execnz .LBB7_1
@@ -296,26 +304,28 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16_vgpr_descr(i32 %node_p
;
; GFX1013-LABEL: image_bvh_intersect_ray_a16_vgpr_descr:
; GFX1013: ; %bb.0:
-; GFX1013-NEXT: v_lshrrev_b32_e32 v13, 16, v5
-; GFX1013-NEXT: v_and_b32_e32 v14, 0xffff, v7
+; GFX1013-NEXT: v_mov_b32_e32 v17, v9
+; GFX1013-NEXT: v_mov_b32_e32 v18, v10
+; GFX1013-NEXT: v_lshrrev_b32_e32 v9, 16, v5
+; GFX1013-NEXT: v_and_b32_e32 v10, 0xffff, v7
; GFX1013-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX1013-NEXT: s_mov_b32 s1, exec_lo
-; GFX1013-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX1013-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX1013-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX1013-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX1013-NEXT: v_alignbit_b32 v7, v8, v7, 16
-; GFX1013-NEXT: v_and_or_b32 v5, 0xffff, v5, v13
-; GFX1013-NEXT: v_and_or_b32 v6, 0xffff, v6, v14
+; GFX1013-NEXT: v_and_or_b32 v5, 0xffff, v5, v9
+; GFX1013-NEXT: v_and_or_b32 v6, 0xffff, v6, v10
; GFX1013-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1
-; GFX1013-NEXT: v_readfirstlane_b32 s4, v9
-; GFX1013-NEXT: v_readfirstlane_b32 s5, v10
+; GFX1013-NEXT: v_readfirstlane_b32 s4, v17
+; GFX1013-NEXT: v_readfirstlane_b32 s5, v18
; GFX1013-NEXT: v_readfirstlane_b32 s6, v11
; GFX1013-NEXT: v_readfirstlane_b32 s7, v12
-; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[9:10]
+; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[17:18]
; GFX1013-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[11:12]
; GFX1013-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX1013-NEXT: s_and_saveexec_b32 s0, s0
; GFX1013-NEXT: image_bvh_intersect_ray v[13:16], v[0:7], s[4:7] a16
-; GFX1013-NEXT: ; implicit-def: $vgpr9
+; GFX1013-NEXT: ; implicit-def: $vgpr17
; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX1013-NEXT: ; implicit-def: $vgpr9_vgpr10_vgpr11_vgpr12
; GFX1013-NEXT: s_waitcnt_depctr 0xffe3
@@ -333,27 +343,28 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16_vgpr_descr(i32 %node_p
; GFX11-LABEL: image_bvh_intersect_ray_a16_vgpr_descr:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_dual_mov_b32 v16, v0 :: v_dual_mov_b32 v17, v1
-; GFX11-NEXT: v_dual_mov_b32 v15, v4 :: v_dual_and_b32 v0, 0xffff, v7
+; GFX11-NEXT: v_dual_mov_b32 v19, v10 :: v_dual_and_b32 v0, 0xffff, v7
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v8
; GFX11-NEXT: v_dual_mov_b32 v13, v2 :: v_dual_mov_b32 v14, v3
-; GFX11-NEXT: s_mov_b32 s1, exec_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_dual_mov_b32 v15, v4 :: v_dual_mov_b32 v18, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_lshl_or_b32 v4, v5, 16, v0
; GFX11-NEXT: v_perm_b32 v5, v5, v7, 0x7060302
; GFX11-NEXT: v_lshl_or_b32 v6, v6, 16, v1
+; GFX11-NEXT: s_mov_b32 s1, exec_lo
; GFX11-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1
-; GFX11-NEXT: v_readfirstlane_b32 s4, v9
-; GFX11-NEXT: v_readfirstlane_b32 s5, v10
+; GFX11-NEXT: v_readfirstlane_b32 s4, v18
+; GFX11-NEXT: v_readfirstlane_b32 s5, v19
; GFX11-NEXT: v_readfirstlane_b32 s6, v11
; GFX11-NEXT: v_readfirstlane_b32 s7, v12
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[9:10]
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[18:19]
; GFX11-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[11:12]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX11-NEXT: s_and_saveexec_b32 s0, s0
; GFX11-NEXT: image_bvh_intersect_ray v[0:3], [v16, v17, v[13:15], v[4:6]], s[4:7] a16
-; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: ; implicit-def: $vgpr16
; GFX11-NEXT: ; implicit-def: $vgpr17
; GFX11-NEXT: ; implicit-def: $vgpr13_vgpr14_vgpr15
@@ -373,42 +384,44 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16_vgpr_descr(i32 %node_p
define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_vgpr_descr(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr) {
; GFX1030-LABEL: image_bvh64_intersect_ray_vgpr_descr:
; GFX1030: ; %bb.0:
-; GFX1030-NEXT: v_mov_b32_e32 v16, v0
-; GFX1030-NEXT: v_mov_b32_e32 v17, v1
-; GFX1030-NEXT: v_mov_b32_e32 v18, v2
-; GFX1030-NEXT: v_mov_b32_e32 v19, v3
-; GFX1030-NEXT: v_mov_b32_e32 v20, v4
-; GFX1030-NEXT: v_mov_b32_e32 v21, v5
-; GFX1030-NEXT: v_mov_b32_e32 v22, v6
-; GFX1030-NEXT: v_mov_b32_e32 v23, v7
-; GFX1030-NEXT: v_mov_b32_e32 v24, v8
-; GFX1030-NEXT: v_mov_b32_e32 v25, v9
-; GFX1030-NEXT: v_mov_b32_e32 v26, v10
-; GFX1030-NEXT: v_mov_b32_e32 v27, v11
+; GFX1030-NEXT: v_mov_b32_e32 v22, v0
+; GFX1030-NEXT: v_mov_b32_e32 v23, v1
+; GFX1030-NEXT: v_mov_b32_e32 v24, v2
+; GFX1030-NEXT: v_mov_b32_e32 v25, v3
+; GFX1030-NEXT: v_mov_b32_e32 v26, v4
+; GFX1030-NEXT: v_mov_b32_e32 v27, v5
+; GFX1030-NEXT: v_mov_b32_e32 v28, v6
+; GFX1030-NEXT: v_mov_b32_e32 v29, v7
+; GFX1030-NEXT: v_mov_b32_e32 v30, v8
+; GFX1030-NEXT: v_mov_b32_e32 v31, v9
+; GFX1030-NEXT: v_mov_b32_e32 v32, v10
+; GFX1030-NEXT: v_mov_b32_e32 v33, v11
+; GFX1030-NEXT: v_mov_b32_e32 v20, v12
+; GFX1030-NEXT: v_mov_b32_e32 v21, v13
; GFX1030-NEXT: s_mov_b32 s1, exec_lo
; GFX1030-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
-; GFX1030-NEXT: v_readfirstlane_b32 s4, v12
-; GFX1030-NEXT: v_readfirstlane_b32 s5, v13
+; GFX1030-NEXT: v_readfirstlane_b32 s4, v20
+; GFX1030-NEXT: v_readfirstlane_b32 s5, v21
; GFX1030-NEXT: v_readfirstlane_b32 s6, v14
; GFX1030-NEXT: v_readfirstlane_b32 s7, v15
-; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[12:13]
+; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[20:21]
; GFX1030-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[14:15]
; GFX1030-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX1030-NEXT: s_and_saveexec_b32 s0, s0
-; GFX1030-NEXT: image_bvh64_intersect_ray v[0:3], v[16:27], s[4:7]
-; GFX1030-NEXT: ; implicit-def: $vgpr12
-; GFX1030-NEXT: ; implicit-def: $vgpr16
-; GFX1030-NEXT: ; implicit-def: $vgpr17
-; GFX1030-NEXT: ; implicit-def: $vgpr18
-; GFX1030-NEXT: ; implicit-def: $vgpr19
+; GFX1030-NEXT: image_bvh64_intersect_ray v[0:3], v[22:33], s[4:7]
; GFX1030-NEXT: ; implicit-def: $vgpr20
-; GFX1030-NEXT: ; implicit-def: $vgpr21
; GFX1030-NEXT: ; implicit-def: $vgpr22
; GFX1030-NEXT: ; implicit-def: $vgpr23
; GFX1030-NEXT: ; implicit-def: $vgpr24
; GFX1030-NEXT: ; implicit-def: $vgpr25
; GFX1030-NEXT: ; implicit-def: $vgpr26
; GFX1030-NEXT: ; implicit-def: $vgpr27
+; GFX1030-NEXT: ; implicit-def: $vgpr28
+; GFX1030-NEXT: ; implicit-def: $vgpr29
+; GFX1030-NEXT: ; implicit-def: $vgpr30
+; GFX1030-NEXT: ; implicit-def: $vgpr31
+; GFX1030-NEXT: ; implicit-def: $vgpr32
+; GFX1030-NEXT: ; implicit-def: $vgpr33
; GFX1030-NEXT: ; implicit-def: $vgpr12_vgpr13_vgpr14_vgpr15
; GFX1030-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1030-NEXT: s_cbranch_execnz .LBB8_1
@@ -419,18 +432,20 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_vgpr_descr(i64 %node_ptr
;
; GFX1013-LABEL: image_bvh64_intersect_ray_vgpr_descr:
; GFX1013: ; %bb.0:
+; GFX1013-NEXT: v_mov_b32_e32 v20, v12
+; GFX1013-NEXT: v_mov_b32_e32 v21, v13
; GFX1013-NEXT: s_mov_b32 s1, exec_lo
; GFX1013-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
-; GFX1013-NEXT: v_readfirstlane_b32 s4, v12
-; GFX1013-NEXT: v_readfirstlane_b32 s5, v13
+; GFX1013-NEXT: v_readfirstlane_b32 s4, v20
+; GFX1013-NEXT: v_readfirstlane_b32 s5, v21
; GFX1013-NEXT: v_readfirstlane_b32 s6, v14
; GFX1013-NEXT: v_readfirstlane_b32 s7, v15
-; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[12:13]
+; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[20:21]
; GFX1013-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[14:15]
; GFX1013-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX1013-NEXT: s_and_saveexec_b32 s0, s0
; GFX1013-NEXT: image_bvh64_intersect_ray v[16:19], v[0:11], s[4:7]
-; GFX1013-NEXT: ; implicit-def: $vgpr12
+; GFX1013-NEXT: ; implicit-def: $vgpr20
; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11
; GFX1013-NEXT: ; implicit-def: $vgpr12_vgpr13_vgpr14_vgpr15
; GFX1013-NEXT: s_waitcnt_depctr 0xffe3
@@ -450,20 +465,22 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_vgpr_descr(i64 %node_ptr
; GFX11-NEXT: v_dual_mov_b32 v19, v0 :: v_dual_mov_b32 v20, v1
; GFX11-NEXT: v_dual_mov_b32 v21, v2 :: v_dual_mov_b32 v16, v3
; GFX11-NEXT: v_dual_mov_b32 v17, v4 :: v_dual_mov_b32 v18, v5
+; GFX11-NEXT: v_dual_mov_b32 v4, v12 :: v_dual_mov_b32 v5, v13
; GFX11-NEXT: s_mov_b32 s1, exec_lo
; GFX11-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
-; GFX11-NEXT: v_readfirstlane_b32 s4, v12
-; GFX11-NEXT: v_readfirstlane_b32 s5, v13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_readfirstlane_b32 s4, v4
+; GFX11-NEXT: v_readfirstlane_b32 s5, v5
; GFX11-NEXT: v_readfirstlane_b32 s6, v14
; GFX11-NEXT: v_readfirstlane_b32 s7, v15
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[12:13]
+;...
[truncated]
|
|
What was the effect of the bug? Was it failing MachineVerifier, or just generating incorrect code? Do you have a small test case? Or do the tests updated in this PR show the fix - and if so, can you point out where? |
Incorrect code for GlobalISel. It was deleting copies from sgpr to vgpr, sdag was moving everything to VALU so it was not affected by this bug. Instruction deletion shows on some very large tests, change is visible in live intervals if you dump them. Will look into writing mir test. |
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petar-avramovic
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Apr 17, 2024
| ; GCN-NEXT: S_BRANCH %bb.42 | ||
| ; GCN-NEXT: {{ $}} | ||
| ; GCN-NEXT: bb.82 (%ir-block.363): | ||
| ; GCN-NEXT: successors: %bb.40(0x80000000) | ||
| ; GCN-NEXT: liveins: $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr33, $vgpr0, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr0_sgpr1_sgpr2_sgpr3 | ||
| ; GCN-NEXT: {{ $}} | ||
| ; GCN-NEXT: renamable $sgpr14 = S_OR_B32 renamable $sgpr33, 2, implicit-def dead $scc | ||
| ; GCN-NEXT: renamable $vgpr3 = COPY killed renamable $sgpr14 |
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this $vgpr3
petar-avramovic
commented
Apr 17, 2024
| ; GCN-NEXT: renamable $vgpr3 = COPY killed renamable $sgpr14 | ||
| ; GCN-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF | ||
| ; GCN-NEXT: renamable $vgpr1_vgpr2 = IMPLICIT_DEF | ||
| ; GCN-NEXT: renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF |
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is overwritten by implicit def here
petar-avramovic
commented
Apr 17, 2024
| ; GCN-NEXT: renamable $vgpr15 = COPY killed renamable $sgpr14 | ||
| ; GCN-NEXT: renamable $vgpr9_vgpr10 = IMPLICIT_DEF | ||
| ; GCN-NEXT: renamable $vgpr13_vgpr14 = IMPLICIT_DEF | ||
| ; GCN-NEXT: renamable $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8 = IMPLICIT_DEF |
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copy is in $vgpr15, no overwrite
arsenm
reviewed
Apr 17, 2024
| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 | ||
| # RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1010 -start-before=rename-independent-subregs -stop-before=amdgpu-mark-last-scratch-load %s -o - | FileCheck -check-prefix=GCN %s | ||
|
|
||
| --- | |
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This test needs to be reduced, preferably to something which doesn't require an IR or registers section and at most a handful of blocks
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| ; DeadInstDelete-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF | ||
| ; DeadInstDelete-NEXT: renamable $vgpr1_vgpr2 = IMPLICIT_DEF | ||
| ; DeadInstDelete-NEXT: renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF | ||
| ; DeadInstDelete-NEXT: renamable $vgpr15 = COPY killed renamable $sgpr15 |
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Added run line that shows instruction that was deleted.
Here, after the change, it is not deleted.
For context this is lowered divergent phi with uniform inputs, inputs stayed in sgpr but copy to vgpr(phi itself) got deleted because it became dead after register allocator that did not have correct live intervals information.
arsenm
reviewed
Apr 19, 2024
| successors: %bb.82(0x40000000), %bb.40(0x40000000) | ||
| liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2 | ||
|
|
||
| %11:vgpr_32 = COPY $vgpr0 |
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Can you shrink this down any more? Also, use run-pass=none to compact the register numbers
arsenm
reviewed
Apr 22, 2024
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| # RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1010 -start-before=rename-independent-subregs -mattr=-wavefrontsize32,+wavefrontsize64 -stop-before=amdgpu-mark-last-scratch-load %s -o - | FileCheck -check-prefix=RegAlloc %s | ||
| # RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1010 -start-before=rename-independent-subregs -mattr=-wavefrontsize32,+wavefrontsize64 -stop-after=machine-cp %s -o - | FileCheck -check-prefix=DeadInstDelete %s |
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You never need -wavefrontsize32
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Check prefixes should also be all caps
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This is shortest I could get it to still expose the bug, live interval fix in RenameIndependentSubregs can be reproduced with fewer instructions but to see effects of that fix, it still needs a couple extra instructions for register allocator to assign registers in such a way to expose the bug due to missing segment for big implicit def in %bb.1. |
arsenm
approved these changes
Apr 23, 2024
Existing sub-ranges are correctly updated because new IMPLICIT_DEF is added, but there is missing sub-range for IMPLICIT_DEF itself. Because of missing sub-range in live-intervals for IMPLICIT_DEF, register allocator does not know that IMPLICIT_DEF rewrites its virtual sub-registers and can end up assigning overlapping physical registers to them. This results in deleting instructions that were defined by sub-registers overwritten by IMPLICIT_DEF as they are now dead.
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Existing sub-ranges are correctly updated because new IMPLICIT_DEF is
added, but there is missing sub-range for IMPLICIT_DEF itself.
Because of missing sub-range in live-intervals for IMPLICIT_DEF,
register allocator does not know that IMPLICIT_DEF rewrites its
virtual sub-registers and can end up assigning overlapping physical
registers to them.
This results in deleting instructions that were defined by sub-registers
overwritten by IMPLICIT_DEF as they are now dead.