Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[RISCV] Check that VLMAX is the same when demanding exact VL #89080

Merged
merged 1 commit into from
Apr 18, 2024

Conversation

lukel97
Copy link
Contributor

@lukel97 lukel97 commented Apr 17, 2024

Currently we just check the AVL is the same, but if the AVL is larger than VLMAX then the VL may differ. We need to also check that the VLMAX (a.k.a the SEW/LMUL ratio) is also the same.

This doesn't seem to be a problem in practice beacause coincidentally we only demanded VLAny whenever we also demand SEWLMULRatio, see getDemanded. So I don't think it's possible to create a test case.

Currently we just check the AVL is the same, but if the AVL is larger than VLMAX then the VL may differ. We need to also check that the VLMAX (a.k.a the SEW/LMUL ratio) is also the same.

This doesn't seem to be a problem in practice beacause coincidentally we only demanded VLAny whenever we also demand SEWLMULRatio, see getDemanded. So I don't think it's possible to create a test case.
@llvmbot
Copy link
Collaborator

llvmbot commented Apr 17, 2024

@llvm/pr-subscribers-backend-risc-v

Author: Luke Lau (lukel97)

Changes

Currently we just check the AVL is the same, but if the AVL is larger than VLMAX then the VL may differ. We need to also check that the VLMAX (a.k.a the SEW/LMUL ratio) is also the same.

This doesn't seem to be a problem in practice beacause coincidentally we only demanded VLAny whenever we also demand SEWLMULRatio, see getDemanded. So I don't think it's possible to create a test case.


Full diff: https://github.com/llvm/llvm-project/pull/89080.diff

1 Files Affected:

  • (modified) llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp (+1-1)
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index fa37d1ccccd737..331253e39c0acb 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -616,7 +616,7 @@ class VSETVLIInfo {
     if (SEWLMULRatioOnly)
       return false;
 
-    if (Used.VLAny && !hasSameAVL(Require))
+    if (Used.VLAny && !(hasSameAVL(Require) && hasSameVLMAX(Require)))
       return false;
 
     if (Used.VLZeroness && !hasEquallyZeroAVL(Require, MRI))

Copy link
Contributor

@BeMg BeMg left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM

@lukel97 lukel97 merged commit 3fbb815 into llvm:main Apr 18, 2024
5 of 6 checks passed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
Development

Successfully merging this pull request may close these issues.

None yet

3 participants