[SystemZ] Add TPEI instruction and Associated Facility #89372
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@llvm/pr-subscribers-backend-systemz @llvm/pr-subscribers-mc Author: Dominik Steenken (dominik-steenken) ChangesThis PR adds the TPEI (Test Pending External Interruption) instruction, along with the facility that contains it. This is a millicoded system instruction that is not used for code generation, so it will be used exclusively by the Assembler and Disassembler. Full diff: https://github.com/llvm/llvm-project/pull/89372.diff 8 Files Affected:
diff --git a/llvm/lib/Target/SystemZ/SystemZFeatures.td b/llvm/lib/Target/SystemZ/SystemZFeatures.td
index a1e2a92b40ac23..e6b95d32c29fad 100644
--- a/llvm/lib/Target/SystemZ/SystemZFeatures.td
+++ b/llvm/lib/Target/SystemZ/SystemZFeatures.td
@@ -246,6 +246,11 @@ def FeatureInsertReferenceBitsMultiple : SystemZFeature<
"Assume that the insert-reference-bits-multiple facility is installed"
>;
+def FeatureTestPendingExternalInterruption : SystemZFeature<
+ "test-pending-external-interruption", "TestPendingExternalInterruption", (all_of FeatureTestPendingExternalInterruption),
+ "Assume that the test-pending-external-interruption facility is installed"
+>;
+
def Arch12NewFeatures : SystemZFeatureList<[
FeatureMiscellaneousExtensions2,
FeatureGuardedStorage,
@@ -253,7 +258,8 @@ def Arch12NewFeatures : SystemZFeatureList<[
FeatureMessageSecurityAssist8,
FeatureVectorEnhancements1,
FeatureVectorPackedDecimal,
- FeatureInsertReferenceBitsMultiple
+ FeatureInsertReferenceBitsMultiple,
+ FeatureTestPendingExternalInterruption
]>;
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrSystem.td b/llvm/lib/Target/SystemZ/SystemZInstrSystem.td
index 497844bec85d17..1f153cc92bb9c8 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrSystem.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrSystem.td
@@ -541,6 +541,10 @@ let hasSideEffects = 1, Defs = [CC] in
let hasSideEffects = 1, Defs = [CC] in
def TPI : StoreInherentS<"tpi", 0xB236, null_frag, 0>;
+// Test pending external interruption.
+let hasSideEffects = 1, Defs = [CC], Predicates = [FeatureTestPendingExternalInterruption] in
+ def TPEI : UnaryRRE<"tpei", 0xB9A1, null_frag, GR64, GR64>;
+
// Set address limit.
let hasSideEffects = 1, Uses = [R1L] in
def SAL : SideEffectInherentS<"sal", 0xB237, null_frag>;
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
index 7e6302ae656743..120d4a457ee396 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
@@ -1640,7 +1640,7 @@ def : InstRW<[WLat30, MCD], (instregex "(M|S|ST|T)SCH$")>;
def : InstRW<[WLat30, MCD], (instregex "RCHP$")>;
def : InstRW<[WLat30, MCD], (instregex "SCHM$")>;
def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
-def : InstRW<[WLat30, MCD], (instregex "TPI$")>;
+def : InstRW<[WLat30, MCD], (instregex "TPE?I$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
}
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
index 89edcf426bd714..acba3a1fd9919e 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
@@ -1686,7 +1686,7 @@ def : InstRW<[WLat30, MCD], (instregex "(M|S|ST|T)SCH$")>;
def : InstRW<[WLat30, MCD], (instregex "RCHP$")>;
def : InstRW<[WLat30, MCD], (instregex "SCHM$")>;
def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
-def : InstRW<[WLat30, MCD], (instregex "TPI$")>;
+def : InstRW<[WLat30, MCD], (instregex "TPE?I$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
}
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
index 8f6dc3befc1976..dd82b2b9b71e75 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
@@ -1719,7 +1719,7 @@ def : InstRW<[WLat30, MCD], (instregex "(M|S|ST|T)SCH$")>;
def : InstRW<[WLat30, MCD], (instregex "RCHP$")>;
def : InstRW<[WLat30, MCD], (instregex "SCHM$")>;
def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
-def : InstRW<[WLat30, MCD], (instregex "TPI$")>;
+def : InstRW<[WLat30, MCD], (instregex "TPE?I$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
}
diff --git a/llvm/test/MC/Disassembler/SystemZ/insns-z14.txt b/llvm/test/MC/Disassembler/SystemZ/insns-z14.txt
index c73b50c1c2fbdc..f1657bdea84d17 100644
--- a/llvm/test/MC/Disassembler/SystemZ/insns-z14.txt
+++ b/llvm/test/MC/Disassembler/SystemZ/insns-z14.txt
@@ -3251,3 +3251,11 @@
# CHECK: wftcixb %v4, %v21, 1656
0xe7 0x45 0x67 0x88 0x44 0x4a
+# CHECK: tpei %r0, %r15
+0xb9 0xa1 0x00 0x0f
+
+# CHECK: tpei %r15, %r0
+0xb9 0xa1 0x00 0xf0
+
+# CHECK: tpei %r4, %r10
+0xb9 0xa1 0x00 0x4a
diff --git a/llvm/test/MC/SystemZ/insn-bad-z13.s b/llvm/test/MC/SystemZ/insn-bad-z13.s
index 4ae4fd99fbd4dc..d126063bc4b445 100644
--- a/llvm/test/MC/SystemZ/insn-bad-z13.s
+++ b/llvm/test/MC/SystemZ/insn-bad-z13.s
@@ -3024,3 +3024,6 @@
wledb %v0, %v0, -1, 0
wledb %v0, %v0, 16, 0
+ #CHECK: error: instruction requires: test-pending-external-interrupt
+ #CHECK: tpei %r0, %r1
+ tpei %r0, %r1
\ No newline at end of file
diff --git a/llvm/test/MC/SystemZ/insn-good-z14.s b/llvm/test/MC/SystemZ/insn-good-z14.s
index ec12283ecbae89..385fd3ce7d4267 100644
--- a/llvm/test/MC/SystemZ/insn-good-z14.s
+++ b/llvm/test/MC/SystemZ/insn-good-z14.s
@@ -2720,3 +2720,9 @@
wftcixb %v31, %v0, 0
wftcixb %v4, %v21, 0x678
+#CHECK: tpei %r0, %r15 # encoding: [0xb9,0xa1,0x00,0x0f]
+#CHECK: tpei %r15, %r0 # encoding: [0xb9,0xa1,0x00,0xf0]
+#CHECK: tpei %r4, %r10 # encoding: [0xb9,0xa1,0x00,0x4a]
+ tpei %r0, %r15
+ tpei %r15, %r0
+ tpei %r4, %r10
|
|
@uweigand FYI |
uweigand
reviewed
Apr 19, 2024
llvm/test/MC/SystemZ/insn-bad-z13.s
Outdated
| @@ -3024,3 +3024,6 @@ | |||
| wledb %v0, %v0, -1, 0 | |||
| wledb %v0, %v0, 16, 0 | |||
|
|
|||
| #CHECK: error: instruction requires: test-pending-external-interrupt | |||
| #CHECK: tpei %r0, %r1 | |||
| tpei %r0, %r1 | |||
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should be fixed now.
This commit adds the TPEI (Test Pending External Interruption) instruction, along with the facility that contains it. This is a millicoded system instruction that is not used for code generation, so it will be used exclusively by the Assembler and Disassembler. Accordingly, this commit also adds tests for both.
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This PR adds the TPEI (Test Pending External Interruption) instruction, along with the facility that contains it. This is a millicoded system instruction that is not used for code generation, so it will be used exclusively by the Assembler and Disassembler. Accordingly, this commit also adds tests for both.
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This PR adds the TPEI (Test Pending External Interruption) instruction, along with the facility that contains it. This is a millicoded system instruction that is not used for code generation, so it will be used exclusively by the Assembler and Disassembler.
Accordingly, this commit also adds tests for both.