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[RISCV] Add Sched classes for vector crypto instructions #90068

Merged
merged 5 commits into from
May 3, 2024
Merged

[RISCV] Add Sched classes for vector crypto instructions #90068

merged 5 commits into from
May 3, 2024

Commits on May 3, 2024

  1. [RISCV] Add Sched classes for vector crypto instructions 

    The vector crypto instructions may have different scheduling behavior
compared to VALU operations. Instead of using scheduling resources that
describe VALU operations, we give these instructions their own
scheduling resources. This is similar to what we did for Zb* instructions.

The sifive-p670 has vector crypto, so we model behavior for these instructions
in the P600SchedModel. The numbers are based off of measurements collected
internally. These numbers are a bit old and new measurments show that they may
not be fully accurate. It is likley that we will refine these numbers in a
follow up patch(s) based on new measurments.
    @michaelmaitland
    michaelmaitland committed May 3, 2024
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  2. fixup! fix vandn and vwsll

    @michaelmaitland
    michaelmaitland committed May 3, 2024
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  3. fixup! fix copy paste mistake

    @michaelmaitland
    michaelmaitland committed May 3, 2024
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  4. fixup! fix filename

    @michaelmaitland
    michaelmaitland committed May 3, 2024
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  5. fixup! indentation

    @michaelmaitland
    michaelmaitland committed May 3, 2024
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