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[RISCV] Break the (czero_eqz x, (setne x, 0)) -> x combine into 2 combines. #90428

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Apr 29, 2024
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[RISCV] Break the (czero_eqz x, (setne x, 0)) -> x combine into 2 combines. #90428

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[RISCV] Break the (czero_eqz x, (setne x, 0)) -> x combine into 2 com…
topperc Apr 29, 2024
c30f921
fixup! Fix mistakes
topperc Apr 29, 2024
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50 changes: 29 additions & 21 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -16165,28 +16165,36 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
return performSELECTCombine(N, DAG, Subtarget);
case RISCVISD::CZERO_EQZ:
case RISCVISD::CZERO_NEZ: {
SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);
// czero_eq X, (xor Y, 1) -> czero_ne X, Y if Y is 0 or 1.
// czero_ne X, (xor Y, 1) -> czero_eq X, Y if Y is 0 or 1.
if (RHS.getOpcode() == ISD::XOR && isOneConstant(RHS.getOperand(1))) {
SDValue Cond = RHS.getOperand(0);
APInt Mask = APInt::getBitsSetFrom(Cond.getValueSizeInBits(), 1);
if (DAG.MaskedValueIsZero(Cond, Mask)) {
unsigned NewOpc = N->getOpcode() == RISCVISD::CZERO_EQZ
? RISCVISD::CZERO_NEZ
: RISCVISD::CZERO_EQZ;
return DAG.getNode(NewOpc, SDLoc(N), N->getValueType(0), LHS, Cond);
}
SDValue Val = N->getOperand(0);
SDValue Cond = N->getOperand(1);

unsigned Opc = N->getOpcode();

// czero_eqz x, x -> x
if (Opc == RISCVISD::CZERO_EQZ && Val == Cond)
return Val;

unsigned InvOpc =
Opc == RISCVISD::CZERO_EQZ ? RISCVISD::CZERO_NEZ : RISCVISD::CZERO_EQZ;

// czero_eqz X, (xor Y, 1) -> czero_nez X, Y if Y is 0 or 1.
// czero_nez X, (xor Y, 1) -> czero_eqz X, Y if Y is 0 or 1.
if (Cond.getOpcode() == ISD::XOR && isOneConstant(Cond.getOperand(1))) {
SDValue NewCond = Cond.getOperand(0);
APInt Mask = APInt::getBitsSetFrom(NewCond.getValueSizeInBits(), 1);
if (DAG.MaskedValueIsZero(NewCond, Mask))
return DAG.getNode(InvOpc, SDLoc(N), N->getValueType(0), Val, NewCond);
}
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// czero_eqz x, (setcc y, 0, ne) -> czero_eqz x, y
// czero_nez x, (setcc y, 0, ne) -> czero_nez x, y
// czero_eqz x, (setcc y, 0, eq) -> czero_nez x, y
// czero_nez x, (setcc y, 0, eq) -> czero_eqz x, y
if (Cond.getOpcode() == ISD::SETCC && isNullConstant(Cond.getOperand(1))) {
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I think the following logic can be removed now.

llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td

Lines 42 to 49 in 3785d74

def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_setne (XLenVT GPR:$rc)))),
(CZERO_EQZ GPR:$rs1, GPR:$rc)>;
def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_seteq (XLenVT GPR:$rc)))),
(CZERO_NEZ GPR:$rs1, GPR:$rc)>;
def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, (riscv_setne (XLenVT GPR:$rc)))),
(CZERO_NEZ GPR:$rs1, GPR:$rc)>;
def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, (riscv_seteq (XLenVT GPR:$rc)))),
(CZERO_EQZ GPR:$rs1, GPR:$rc)>;

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Those can't remove removed. They handle cases other than RHS being 0.

ISD::CondCode CCVal = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
if (ISD::isIntEqualitySetCC(CCVal))
return DAG.getNode(CCVal == ISD::SETNE ? Opc : InvOpc, SDLoc(N),
N->getValueType(0), Val, Cond.getOperand(0));
}
// czero_eqz x, (setcc x, 0, ne) -> x
// czero_nez x, (setcc x, 0, eq) -> x
if (RHS.getOpcode() == ISD::SETCC && isNullConstant(RHS.getOperand(1)) &&
cast<CondCodeSDNode>(RHS.getOperand(2))->get() ==
(N->getOpcode() == RISCVISD::CZERO_EQZ ? ISD::CondCode::SETNE
: ISD::CondCode::SETEQ) &&
LHS == RHS.getOperand(0))
return LHS;
return SDValue();
}
case RISCVISD::SELECT_CC: {
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