[AMDGPU] Check MIR after SIMemoryLegalizer instead of final ISA #90601
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Since llvm#72830 the memory legalizer tests have not shown s_waitcnt instructions inserted by SIMemoryLegalizer because they have mostly been removed by SIInsertWaitcnts. Checking the MIR immediately after SIMemoryLegalizer runs fixes this so you can see exactly what the pass has inserted.
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@llvm/pr-subscribers-backend-amdgpu Author: Jay Foad (jayfoad) ChangesSince #72830 the memory legalizer tests have not shown s_waitcnt Checking the MIR immediately after SIMemoryLegalizer runs fixes this so Patch is 29.32 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/90601.diff 27 Files Affected:
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll
index e13542f61474e2..a169753f532b57 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll
@@ -1,2563 +1,3063 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 < %s | FileCheck --check-prefixes=GFX6 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck --check-prefixes=GFX7 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck --check-prefixes=GFX10-WGP %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode < %s | FileCheck --check-prefixes=GFX10-CU %s
-; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx700 -amdgcn-skip-cache-invalidations < %s | FileCheck --check-prefixes=SKIP-CACHE-INV %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX90A-NOTTGSPLIT %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -mattr=+tgsplit < %s | FileCheck -check-prefixes=GFX90A-TGSPLIT %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx940 < %s | FileCheck -check-prefixes=GFX940-NOTTGSPLIT %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx940 -mattr=+tgsplit < %s | FileCheck -check-prefixes=GFX940-TGSPLIT %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck --check-prefixes=GFX11-WGP %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+cumode < %s | FileCheck --check-prefixes=GFX11-CU %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GFX12-WGP %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+cumode < %s | FileCheck --check-prefixes=GFX12-CU %s
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=si-memory-legalizer -mcpu=gfx600 < %s | FileCheck --check-prefixes=GFX6 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=si-memory-legalizer -mcpu=gfx700 < %s | FileCheck --check-prefixes=GFX7 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=si-memory-legalizer -mcpu=gfx1010 < %s | FileCheck --check-prefixes=GFX10-WGP %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=si-memory-legalizer -mcpu=gfx1010 -mattr=+cumode < %s | FileCheck --check-prefixes=GFX10-CU %s
+; RUN: llc -mtriple=amdgcn-amd-amdpal -stop-after=si-memory-legalizer -mcpu=gfx700 -amdgcn-skip-cache-invalidations < %s | FileCheck --check-prefixes=SKIP-CACHE-INV %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=si-memory-legalizer -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX90A-NOTTGSPLIT %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=si-memory-legalizer -mcpu=gfx90a -mattr=+tgsplit < %s | FileCheck -check-prefixes=GFX90A-TGSPLIT %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=si-memory-legalizer -mcpu=gfx940 < %s | FileCheck -check-prefixes=GFX940-NOTTGSPLIT %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=si-memory-legalizer -mcpu=gfx940 -mattr=+tgsplit < %s | FileCheck -check-prefixes=GFX940-TGSPLIT %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=si-memory-legalizer -mcpu=gfx1100 < %s | FileCheck --check-prefixes=GFX11-WGP %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=si-memory-legalizer -mcpu=gfx1100 -mattr=+cumode < %s | FileCheck --check-prefixes=GFX11-CU %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=si-memory-legalizer -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GFX12-WGP %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=si-memory-legalizer -mcpu=gfx1200 -mattr=+cumode < %s | FileCheck --check-prefixes=GFX12-CU %s
define amdgpu_kernel void @singlethread_acquire_fence() {
-; GFX6-LABEL: singlethread_acquire_fence:
-; GFX6: ; %bb.0: ; %entry
-; GFX6-NEXT: s_endpgm
-;
-; GFX7-LABEL: singlethread_acquire_fence:
-; GFX7: ; %bb.0: ; %entry
-; GFX7-NEXT: s_endpgm
-;
-; GFX10-WGP-LABEL: singlethread_acquire_fence:
-; GFX10-WGP: ; %bb.0: ; %entry
-; GFX10-WGP-NEXT: s_endpgm
-;
-; GFX10-CU-LABEL: singlethread_acquire_fence:
-; GFX10-CU: ; %bb.0: ; %entry
-; GFX10-CU-NEXT: s_endpgm
-;
-; SKIP-CACHE-INV-LABEL: singlethread_acquire_fence:
-; SKIP-CACHE-INV: ; %bb.0: ; %entry
-; SKIP-CACHE-INV-NEXT: s_endpgm
-;
-; GFX90A-NOTTGSPLIT-LABEL: singlethread_acquire_fence:
-; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
-; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
-;
-; GFX90A-TGSPLIT-LABEL: singlethread_acquire_fence:
-; GFX90A-TGSPLIT: ; %bb.0: ; %entry
-; GFX90A-TGSPLIT-NEXT: s_endpgm
-;
-; GFX940-NOTTGSPLIT-LABEL: singlethread_acquire_fence:
-; GFX940-NOTTGSPLIT: ; %bb.0: ; %entry
-; GFX940-NOTTGSPLIT-NEXT: s_endpgm
-;
-; GFX940-TGSPLIT-LABEL: singlethread_acquire_fence:
-; GFX940-TGSPLIT: ; %bb.0: ; %entry
-; GFX940-TGSPLIT-NEXT: s_endpgm
-;
-; GFX11-WGP-LABEL: singlethread_acquire_fence:
-; GFX11-WGP: ; %bb.0: ; %entry
-; GFX11-WGP-NEXT: s_endpgm
-;
-; GFX11-CU-LABEL: singlethread_acquire_fence:
-; GFX11-CU: ; %bb.0: ; %entry
-; GFX11-CU-NEXT: s_endpgm
-;
-; GFX12-WGP-LABEL: singlethread_acquire_fence:
-; GFX12-WGP: ; %bb.0: ; %entry
-; GFX12-WGP-NEXT: s_endpgm
-;
-; GFX12-CU-LABEL: singlethread_acquire_fence:
-; GFX12-CU: ; %bb.0: ; %entry
-; GFX12-CU-NEXT: s_endpgm
+ ; GFX6-LABEL: name: singlethread_acquire_fence
+ ; GFX6: bb.0.entry:
+ ; GFX6-NEXT: S_ENDPGM 0
+ ;
+ ; GFX7-LABEL: name: singlethread_acquire_fence
+ ; GFX7: bb.0.entry:
+ ; GFX7-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10-WGP-LABEL: name: singlethread_acquire_fence
+ ; GFX10-WGP: bb.0.entry:
+ ; GFX10-WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10-CU-LABEL: name: singlethread_acquire_fence
+ ; GFX10-CU: bb.0.entry:
+ ; GFX10-CU-NEXT: S_ENDPGM 0
+ ;
+ ; SKIP-CACHE-INV-LABEL: name: singlethread_acquire_fence
+ ; SKIP-CACHE-INV: bb.0.entry:
+ ; SKIP-CACHE-INV-NEXT: S_ENDPGM 0
+ ;
+ ; GFX90A-NOTTGSPLIT-LABEL: name: singlethread_acquire_fence
+ ; GFX90A-NOTTGSPLIT: bb.0.entry:
+ ; GFX90A-NOTTGSPLIT-NEXT: S_ENDPGM 0
+ ;
+ ; GFX90A-TGSPLIT-LABEL: name: singlethread_acquire_fence
+ ; GFX90A-TGSPLIT: bb.0.entry:
+ ; GFX90A-TGSPLIT-NEXT: S_ENDPGM 0
+ ;
+ ; GFX940-NOTTGSPLIT-LABEL: name: singlethread_acquire_fence
+ ; GFX940-NOTTGSPLIT: bb.0.entry:
+ ; GFX940-NOTTGSPLIT-NEXT: S_ENDPGM 0
+ ;
+ ; GFX940-TGSPLIT-LABEL: name: singlethread_acquire_fence
+ ; GFX940-TGSPLIT: bb.0.entry:
+ ; GFX940-TGSPLIT-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11-WGP-LABEL: name: singlethread_acquire_fence
+ ; GFX11-WGP: bb.0.entry:
+ ; GFX11-WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11-CU-LABEL: name: singlethread_acquire_fence
+ ; GFX11-CU: bb.0.entry:
+ ; GFX11-CU-NEXT: S_ENDPGM 0
+ ;
+ ; GFX12-WGP-LABEL: name: singlethread_acquire_fence
+ ; GFX12-WGP: bb.0.entry:
+ ; GFX12-WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX12-CU-LABEL: name: singlethread_acquire_fence
+ ; GFX12-CU: bb.0.entry:
+ ; GFX12-CU-NEXT: S_ENDPGM 0
entry:
fence syncscope("singlethread") acquire
ret void
}
define amdgpu_kernel void @singlethread_release_fence() {
-; GFX6-LABEL: singlethread_release_fence:
-; GFX6: ; %bb.0: ; %entry
-; GFX6-NEXT: s_endpgm
-;
-; GFX7-LABEL: singlethread_release_fence:
-; GFX7: ; %bb.0: ; %entry
-; GFX7-NEXT: s_endpgm
-;
-; GFX10-WGP-LABEL: singlethread_release_fence:
-; GFX10-WGP: ; %bb.0: ; %entry
-; GFX10-WGP-NEXT: s_endpgm
-;
-; GFX10-CU-LABEL: singlethread_release_fence:
-; GFX10-CU: ; %bb.0: ; %entry
-; GFX10-CU-NEXT: s_endpgm
-;
-; SKIP-CACHE-INV-LABEL: singlethread_release_fence:
-; SKIP-CACHE-INV: ; %bb.0: ; %entry
-; SKIP-CACHE-INV-NEXT: s_endpgm
-;
-; GFX90A-NOTTGSPLIT-LABEL: singlethread_release_fence:
-; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
-; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
-;
-; GFX90A-TGSPLIT-LABEL: singlethread_release_fence:
-; GFX90A-TGSPLIT: ; %bb.0: ; %entry
-; GFX90A-TGSPLIT-NEXT: s_endpgm
-;
-; GFX940-NOTTGSPLIT-LABEL: singlethread_release_fence:
-; GFX940-NOTTGSPLIT: ; %bb.0: ; %entry
-; GFX940-NOTTGSPLIT-NEXT: s_endpgm
-;
-; GFX940-TGSPLIT-LABEL: singlethread_release_fence:
-; GFX940-TGSPLIT: ; %bb.0: ; %entry
-; GFX940-TGSPLIT-NEXT: s_endpgm
-;
-; GFX11-WGP-LABEL: singlethread_release_fence:
-; GFX11-WGP: ; %bb.0: ; %entry
-; GFX11-WGP-NEXT: s_endpgm
-;
-; GFX11-CU-LABEL: singlethread_release_fence:
-; GFX11-CU: ; %bb.0: ; %entry
-; GFX11-CU-NEXT: s_endpgm
-;
-; GFX12-WGP-LABEL: singlethread_release_fence:
-; GFX12-WGP: ; %bb.0: ; %entry
-; GFX12-WGP-NEXT: s_endpgm
-;
-; GFX12-CU-LABEL: singlethread_release_fence:
-; GFX12-CU: ; %bb.0: ; %entry
-; GFX12-CU-NEXT: s_endpgm
+ ; GFX6-LABEL: name: singlethread_release_fence
+ ; GFX6: bb.0.entry:
+ ; GFX6-NEXT: S_ENDPGM 0
+ ;
+ ; GFX7-LABEL: name: singlethread_release_fence
+ ; GFX7: bb.0.entry:
+ ; GFX7-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10-WGP-LABEL: name: singlethread_release_fence
+ ; GFX10-WGP: bb.0.entry:
+ ; GFX10-WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10-CU-LABEL: name: singlethread_release_fence
+ ; GFX10-CU: bb.0.entry:
+ ; GFX10-CU-NEXT: S_ENDPGM 0
+ ;
+ ; SKIP-CACHE-INV-LABEL: name: singlethread_release_fence
+ ; SKIP-CACHE-INV: bb.0.entry:
+ ; SKIP-CACHE-INV-NEXT: S_ENDPGM 0
+ ;
+ ; GFX90A-NOTTGSPLIT-LABEL: name: singlethread_release_fence
+ ; GFX90A-NOTTGSPLIT: bb.0.entry:
+ ; GFX90A-NOTTGSPLIT-NEXT: S_ENDPGM 0
+ ;
+ ; GFX90A-TGSPLIT-LABEL: name: singlethread_release_fence
+ ; GFX90A-TGSPLIT: bb.0.entry:
+ ; GFX90A-TGSPLIT-NEXT: S_ENDPGM 0
+ ;
+ ; GFX940-NOTTGSPLIT-LABEL: name: singlethread_release_fence
+ ; GFX940-NOTTGSPLIT: bb.0.entry:
+ ; GFX940-NOTTGSPLIT-NEXT: S_ENDPGM 0
+ ;
+ ; GFX940-TGSPLIT-LABEL: name: singlethread_release_fence
+ ; GFX940-TGSPLIT: bb.0.entry:
+ ; GFX940-TGSPLIT-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11-WGP-LABEL: name: singlethread_release_fence
+ ; GFX11-WGP: bb.0.entry:
+ ; GFX11-WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11-CU-LABEL: name: singlethread_release_fence
+ ; GFX11-CU: bb.0.entry:
+ ; GFX11-CU-NEXT: S_ENDPGM 0
+ ;
+ ; GFX12-WGP-LABEL: name: singlethread_release_fence
+ ; GFX12-WGP: bb.0.entry:
+ ; GFX12-WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX12-CU-LABEL: name: singlethread_release_fence
+ ; GFX12-CU: bb.0.entry:
+ ; GFX12-CU-NEXT: S_ENDPGM 0
entry:
fence syncscope("singlethread") release
ret void
}
define amdgpu_kernel void @singlethread_acq_rel_fence() {
-; GFX6-LABEL: singlethread_acq_rel_fence:
-; GFX6: ; %bb.0: ; %entry
-; GFX6-NEXT: s_endpgm
-;
-; GFX7-LABEL: singlethread_acq_rel_fence:
-; GFX7: ; %bb.0: ; %entry
-; GFX7-NEXT: s_endpgm
-;
-; GFX10-WGP-LABEL: singlethread_acq_rel_fence:
-; GFX10-WGP: ; %bb.0: ; %entry
-; GFX10-WGP-NEXT: s_endpgm
-;
-; GFX10-CU-LABEL: singlethread_acq_rel_fence:
-; GFX10-CU: ; %bb.0: ; %entry
-; GFX10-CU-NEXT: s_endpgm
-;
-; SKIP-CACHE-INV-LABEL: singlethread_acq_rel_fence:
-; SKIP-CACHE-INV: ; %bb.0: ; %entry
-; SKIP-CACHE-INV-NEXT: s_endpgm
-;
-; GFX90A-NOTTGSPLIT-LABEL: singlethread_acq_rel_fence:
-; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
-; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
-;
-; GFX90A-TGSPLIT-LABEL: singlethread_acq_rel_fence:
-; GFX90A-TGSPLIT: ; %bb.0: ; %entry
-; GFX90A-TGSPLIT-NEXT: s_endpgm
-;
-; GFX940-NOTTGSPLIT-LABEL: singlethread_acq_rel_fence:
-; GFX940-NOTTGSPLIT: ; %bb.0: ; %entry
-; GFX940-NOTTGSPLIT-NEXT: s_endpgm
-;
-; GFX940-TGSPLIT-LABEL: singlethread_acq_rel_fence:
-; GFX940-TGSPLIT: ; %bb.0: ; %entry
-; GFX940-TGSPLIT-NEXT: s_endpgm
-;
-; GFX11-WGP-LABEL: singlethread_acq_rel_fence:
-; GFX11-WGP: ; %bb.0: ; %entry
-; GFX11-WGP-NEXT: s_endpgm
-;
-; GFX11-CU-LABEL: singlethread_acq_rel_fence:
-; GFX11-CU: ; %bb.0: ; %entry
-; GFX11-CU-NEXT: s_endpgm
-;
-; GFX12-WGP-LABEL: singlethread_acq_rel_fence:
-; GFX12-WGP: ; %bb.0: ; %entry
-; GFX12-WGP-NEXT: s_endpgm
-;
-; GFX12-CU-LABEL: singlethread_acq_rel_fence:
-; GFX12-CU: ; %bb.0: ; %entry
-; GFX12-CU-NEXT: s_endpgm
+ ; GFX6-LABEL: name: singlethread_acq_rel_fence
+ ; GFX6: bb.0.entry:
+ ; GFX6-NEXT: S_ENDPGM 0
+ ;
+ ; GFX7-LABEL: name: singlethread_acq_rel_fence
+ ; GFX7: bb.0.entry:
+ ; GFX7-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10-WGP-LABEL: name: singlethread_acq_rel_fence
+ ; GFX10-WGP: bb.0.entry:
+ ; GFX10-WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10-CU-LABEL: name: singlethread_acq_rel_fence
+ ; GFX10-CU: bb.0.entry:
+ ; GFX10-CU-NEXT: S_ENDPGM 0
+ ;
+ ; SKIP-CACHE-INV-LABEL: name: singlethread_acq_rel_fence
+ ; SKIP-CACHE-INV: bb.0.entry:
+ ; SKIP-CACHE-INV-NEXT: S_ENDPGM 0
+ ;
+ ; GFX90A-NOTTGSPLIT-LABEL: name: singlethread_acq_rel_fence
+ ; GFX90A-NOTTGSPLIT: bb.0.entry:
+ ; GFX90A-NOTTGSPLIT-NEXT: S_ENDPGM 0
+ ;
+ ; GFX90A-TGSPLIT-LABEL: name: singlethread_acq_rel_fence
+ ; GFX90A-TGSPLIT: bb.0.entry:
+ ; GFX90A-TGSPLIT-NEXT: S_ENDPGM 0
+ ;
+ ; GFX940-NOTTGSPLIT-LABEL: name: singlethread_acq_rel_fence
+ ; GFX940-NOTTGSPLIT: bb.0.entry:
+ ; GFX940-NOTTGSPLIT-NEXT: S_ENDPGM 0
+ ;
+ ; GFX940-TGSPLIT-LABEL: name: singlethread_acq_rel_fence
+ ; GFX940-TGSPLIT: bb.0.entry:
+ ; GFX940-TGSPLIT-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11-WGP-LABEL: name: singlethread_acq_rel_fence
+ ; GFX11-WGP: bb.0.entry:
+ ; GFX11-WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11-CU-LABEL: name: singlethread_acq_rel_fence
+ ; GFX11-CU: bb.0.entry:
+ ; GFX11-CU-NEXT: S_ENDPGM 0
+ ;
+ ; GFX12-WGP-LABEL: name: singlethread_acq_rel_fence
+ ; GFX12-WGP: bb.0.entry:
+ ; GFX12-WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX12-CU-LABEL: name: singlethread_acq_rel_fence
+ ; GFX12-CU: bb.0.entry:
+ ; GFX12-CU-NEXT: S_ENDPGM 0
entry:
fence syncscope("singlethread") acq_rel
ret void
}
define amdgpu_kernel void @singlethread_seq_cst_fence() {
-; GFX6-LABEL: singlethread_seq_cst_fence:
-; GFX6: ; %bb.0: ; %entry
-; GFX6-NEXT: s_endpgm
-;
-; GFX7-LABEL: singlethread_seq_cst_fence:
-; GFX7: ; %bb.0: ; %entry
-; GFX7-NEXT: s_endpgm
-;
-; GFX10-WGP-LABEL: singlethread_seq_cst_fence:
-; GFX10-WGP: ; %bb.0: ; %entry
-; GFX10-WGP-NEXT: s_endpgm
-;
-; GFX10-CU-LABEL: singlethread_seq_cst_fence:
-; GFX10-CU: ; %bb.0: ; %entry
-; GFX10-CU-NEXT: s_endpgm
-;
-; SKIP-CACHE-INV-LABEL: singlethread_seq_cst_fence:
-; SKIP-CACHE-INV: ; %bb.0: ; %entry
-; SKIP-CACHE-INV-NEXT: s_endpgm
-;
-; GFX90A-NOTTGSPLIT-LABEL: singlethread_seq_cst_fence:
-; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
-; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
-;
-; GFX90A-TGSPLIT-LABEL: singlethread_seq_cst_fence:
-; GFX90A-TGSPLIT: ; %bb.0: ; %entry
-; GFX90A-TGSPLIT-NEXT: s_endpgm
-;
-; GFX940-NOTTGSPLIT-LABEL: singlethread_seq_cst_fence:
-; GFX940-NOTTGSPLIT: ; %bb.0: ; %entry
-; GFX940-NOTTGSPLIT-NEXT: s_endpgm
-;
-; GFX940-TGSPLIT-LABEL: singlethread_seq_cst_fence:
-; GFX940-TGSPLIT: ; %bb.0: ; %entry
-; GFX940-TGSPLIT-NEXT: s_endpgm
-;
-; GFX11-WGP-LABEL: singlethread_seq_cst_fence:
-; GFX11-WGP: ; %bb.0: ; %entry
-; GFX11-WGP-NEXT: s_endpgm
-;
-; GFX11-CU-LABEL: singlethread_seq_cst_fence:
-; GFX11-CU: ; %bb.0: ; %entry
-; GFX11-CU-NEXT: s_endpgm
-;
-; GFX12-WGP-LABEL: singlethread_seq_cst_fence:
-; GFX12-WGP: ; %bb.0: ; %entry
-; GFX12-WGP-NEXT: s_endpgm
-;
-; GFX12-CU-LABEL: singlethread_seq_cst_fence:
-; GFX12-CU: ; %bb.0: ; %entry
-; GFX12-CU-NEXT: s_endpgm
+ ; GFX6-LABEL: name: singlethread_seq_cst_fence
+ ; GFX6: bb.0.entry:
+ ; GFX6-NEXT: S_ENDPGM 0
+ ;
+ ; GFX7-LABEL: name: singlethread_seq_cst_fence
+ ; GFX7: bb.0.entry:
+ ; GFX7-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10-WGP-LABEL: name: singlethread_seq_cst_fence
+ ; GFX10-WGP: bb.0.entry:
+ ; GFX10-WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10-CU-LABEL: name: singlethread_seq_cst_fence
+ ; GFX10-CU: bb.0.entry:
+ ; GFX10-CU-NEXT: S_ENDPGM 0
+ ;
+ ; SKIP-CACHE-INV-LABEL: name: singlethread_seq_cst_fence
+ ; SKIP-CACHE-INV: bb.0.entry:
+ ; SKIP-CACHE-INV-NEXT: S_ENDPGM 0
+ ;
+ ; GFX90A-NOTTGSPLIT-LABEL: name: singlethread_seq_cst_fence
+ ; GFX90A-NOTTGSPLIT: bb.0.entry:
+ ; GFX90A-NOTTGSPLIT-NEXT: S_ENDPGM 0
+ ;
+ ; GFX90A-TGSPLIT-LABEL: name: singlethread_seq_cst_fence
+ ; GFX90A-TGSPLIT: bb.0.entry:
+ ; GFX90A-TGSPLIT-NEXT: S_ENDPGM 0
+ ;
+ ; GFX940-NOTTGSPLIT-LABEL: name: singlethread_seq_cst_fence
+ ; GFX940-NOTTGSPLIT: bb.0.entry:
+ ; GFX940-NOTTGSPLIT-NEXT: S_ENDPGM 0
+ ;
+ ; GFX940-TGSPLIT-LABEL: name: singlethread_seq_cst_fence
+ ; GFX940-TGSPLIT: bb.0.entry:
+ ; GFX940-TGSPLIT-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11-WGP-LABEL: name: singlethread_seq_cst_fence
+ ; GFX11-WGP: bb.0.entry:
+ ; GFX11-WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11-CU-LABEL: name: singlethread_seq_cst_fence
+ ; GFX11-CU: bb.0.entry:
+ ; GFX11-CU-NEXT: S_ENDPGM 0
+ ;
+ ; GFX12-WGP-LABEL: name: singlethread_seq_cst_fence
+ ; GFX12-WGP: bb.0.entry:
+ ; GFX12-WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX12-CU-LABEL: name: singlethread_seq_cst_fence
+ ; GFX12-CU: bb.0.entry:
+ ; GFX12-CU-NEXT: S_ENDPGM 0
entry:
fence syncscope("singlethread") seq_cst
ret void
}
define amdgpu_kernel void @singlethread_one_as_acquire_fence() {
-; GFX6-LABEL: singlethread_one_as_acquire_fence:
-; GFX6: ; %bb.0: ; %entry
-; GFX6-NEXT: s_endpgm
-;
-; GFX7-LABEL: singlethread_one_as_acquire_fence:
-; GFX7: ; %bb.0: ; %entry
-; GFX7-NEXT: s_endpgm
-;
-; GFX10-WGP-LABEL: singlethread_one_as_acquire_fence:
-; GFX10-WGP: ; %bb.0: ; %entry
-; GFX10-WGP-NEXT: s_endpgm
-;
-; GFX10-CU-LABEL: singlethread_one_as_acquire_fence:
-; GFX10-CU: ; %bb.0: ; %entry
-; GFX10-CU-NEXT: s_endpgm
-;
-; SKIP-CACHE-INV-LABEL: singlethread_one_as_acquire_fence:
-; SKIP-CACHE-INV: ; %bb.0: ; %entry
-; SKIP-CACHE-INV-NEXT: s_endpgm
-;
-; GFX90A-NOTTGSPLIT-LABEL: singlethread_one_as_acquire_fence:
-; GFX90A-NOTTGSPLIT: ; %bb.0: ; %entry
-; GFX90A-NOTTGSPLIT-NEXT: s_endpgm
-;
-; GFX90A-TGSPLIT-LABEL: singlethread_one_as_acquire_fence:
-; GFX90A-TGSPLIT: ; %bb.0: ; %entry
-; GFX90A-TGSPLIT-NEXT: s_endpgm
-;
-; GFX940-NOTTGSPLIT-LABEL: singlethread_one_as_acquire_fence:
-; GFX940-NOTTGSPLIT: ; %bb.0: ; %entry
-; GFX940-NOTTGSPLIT-NEXT: s_endpgm
-;
-; GFX940-TGSPLIT-LABEL: singlethread_one_as_acquire_fence:
-; GFX940-TGSPLIT: ; %bb.0: ; %entry
-; GFX940-TGSPLIT-NEXT: s_endpgm
-;
-; GFX11-WGP-LABEL: singlethread_one_as_acquire_fence:
-; GFX11-WGP: ; %bb.0: ; %entry
-; GFX11-WGP-NEXT: s_endpgm
-;
-; GFX11-CU-LABEL: singlethread_one_as_acquire_fence:
-; GFX11-CU: ; %bb.0: ; %entry
-; GFX11-CU-NEXT: s_endpgm
-;
-; GFX12-WGP-LABEL: singlethread_one_as_acquire_fence:
-; GFX12-WGP: ; %bb.0: ; %entry
-; GFX12-WGP-NEXT: s_endpgm
-;
-; GFX12-CU-LABEL: singlethread_one_as_acquire_fence:
-; GFX12-CU: ; %bb.0: ; %entry
-; GFX12-CU-NEXT: s_endpgm
+ ; GFX6-LABEL: name: singlethread_one_as_acquire_fence
+ ; GFX6: bb.0.entry:
+ ; GFX6-NEXT: S_ENDPGM 0
+ ;
+ ; GFX7-LABEL: name: singlethread_one_as_acquire_fence
+ ; GFX7: bb.0.entry:
+ ; GFX7-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10-WGP-LABEL: name: singlethread_one_as_acquire_fence
+ ; GFX10-WGP: bb.0.entry:
+ ; GFX10-WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10-CU-LABEL: name: singlethread_one_as_acquire_fence
+ ; GFX10-CU: bb.0.entry:
+ ; GFX10-CU-NEXT: S_ENDPGM 0
+ ;
+ ; SKIP-CACHE-INV-LABEL: name: singlethread_one_as_acquire_fence
+ ; SKIP-CACHE-INV: bb.0.entry:
+ ; SKIP-CACHE-INV-NEXT: S_ENDPGM 0
+ ;
+ ; GFX90A-NOTTGSPLIT-LABEL: name: singlethread_one_as_acquire_fence
+ ; GFX90A-NOTTGSPLIT: bb.0.entry:
+ ; GFX90A-NOTTGSPLIT-NEXT: S_ENDPGM 0
+ ;
+ ; GFX90A-TGSPLIT-LABEL: name: singlethread_one_as_acquire_fence
+ ; GFX90A-TGSPLIT: bb.0.entry:
+ ; GFX90A-TGSPLIT-NEXT: S_ENDPGM 0
+ ;
+ ; GFX940-NOTTGSPLIT-LABEL: name: singlethread_one_as_acquire_fence
+ ; GFX940-NOTTGSPLIT: bb.0.entry:
+ ; GFX940-NOTTGSPLIT-NEXT: S_ENDPGM 0
+ ;
+ ; GFX940-TGSPLIT-LABEL: name: singlethread_one_as_acquire_fence
+ ; GFX940-TGSPLIT: bb.0.entry:
+ ; GFX940-TGSPLIT-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11-WGP-LABEL: name: singlethread_one_as_acquire_fence
+ ; GFX11-WGP: bb.0.entry:
+ ; GFX11-WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11-CU-LABEL: name: singlethread_one_as_acquire_fence
+ ; GFX11-CU: bb.0.entry:
+ ; GFX11-CU-NEXT: S_ENDPGM 0
+ ;
+ ; GFX12-WGP-...
[truncated]
|
jayfoad
commented
Apr 30, 2024
| ; GFX12-CU-NEXT: s_endpgm | ||
| ; GFX6-LABEL: name: workgroup_acquire_fence | ||
| ; GFX6: bb.0.entry: | ||
| ; GFX6-NEXT: S_WAITCNT_soft 127 |
There was a problem hiding this comment.
Good example here of where all the waitcnts were removed.
|
I am not a fan of the idea to convert all memory legalizer tests to mir. Maybe you can add some specific mir tests instead? |
Well all of As an alternative, how about changing SIInsertWaitcnts so that it does not remove redundant waitcnts at |
I like this much more: we will see what is produced without decoding and it shall work faster too. Now these tests are very slow. |
|
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Since #72830 the memory legalizer tests have not shown s_waitcnt
instructions inserted by SIMemoryLegalizer because they have mostly been
removed by SIInsertWaitcnts.
Checking the MIR immediately after SIMemoryLegalizer runs fixes this so
you can see exactly what the pass has inserted.