[AArch64] NFC: Add RUN lines for streaming-compatible code. #90617
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@llvm/pr-subscribers-backend-aarch64 Author: Sander de Smalen (sdesmalen-arm) ChangesThe intent is to test lowering of vector operations by scalarization, for functions that are streaming-compatible (and thus cannot use NEON) and also don't have the +sve attribute. The generated code is clearly wrong at the moment, but a series of patches will follow to fix up all cases to use scalar instructions. A bit of context: This work will form the base to decouple SME from SVE later on, as it will make sure that no NEON instructions are used in streaming[-compatible] mode. Later this will be followed by a patch that changes Patch is 1.21 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/90617.diff 56 Files Affected:
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-and-combine.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-and-combine.ll
index d81f725eaefca5..fd9259048df543 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-and-combine.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-and-combine.ll
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE
target triple = "aarch64-unknown-linux-gnu"
@@ -14,6 +15,12 @@ define <4 x i8> @vls_sve_and_4xi8(<4 x i8> %b) nounwind {
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: vls_sve_and_4xi8:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: movi d1, #0xff000000ff0000
+; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b
+; NONEON-NOSVE-NEXT: ret
%c = and <4 x i8> %b, <i8 0, i8 255, i8 0, i8 255>
ret <4 x i8> %c
}
@@ -27,6 +34,12 @@ define <8 x i8> @vls_sve_and_8xi8(<8 x i8> %b) nounwind {
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: vls_sve_and_8xi8:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: movi d1, #0xff00ff00ff00ff00
+; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b
+; NONEON-NOSVE-NEXT: ret
%c = and <8 x i8> %b, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
ret <8 x i8> %c
}
@@ -40,6 +53,12 @@ define <16 x i8> @vls_sve_and_16xi8(<16 x i8> %b) nounwind {
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: vls_sve_and_16xi8:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: movi v1.2d, #0xff00ff00ff00ff00
+; NONEON-NOSVE-NEXT: and v0.16b, v0.16b, v1.16b
+; NONEON-NOSVE-NEXT: ret
%c = and <16 x i8> %b, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
ret <16 x i8> %c
}
@@ -56,6 +75,13 @@ define <32 x i8> @vls_sve_and_32xi8(<32 x i8> %ap) nounwind {
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: vls_sve_and_32xi8:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: movi v2.2d, #0xff00ff00ff00ff00
+; NONEON-NOSVE-NEXT: and v0.16b, v0.16b, v2.16b
+; NONEON-NOSVE-NEXT: and v1.16b, v1.16b, v2.16b
+; NONEON-NOSVE-NEXT: ret
%b = and <32 x i8> %ap, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255,
i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
ret <32 x i8> %b
@@ -73,6 +99,13 @@ define <2 x i16> @vls_sve_and_2xi16(<2 x i16> %b) nounwind {
; CHECK-NEXT: ldr d0, [sp, #8]
; CHECK-NEXT: add sp, sp, #16
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: vls_sve_and_2xi16:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0
+; NONEON-NOSVE-NEXT: mov v0.s[0], wzr
+; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0
+; NONEON-NOSVE-NEXT: ret
%c = and <2 x i16> %b, <i16 0, i16 65535>
ret <2 x i16> %c
}
@@ -86,6 +119,12 @@ define <4 x i16> @vls_sve_and_4xi16(<4 x i16> %b) nounwind {
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: vls_sve_and_4xi16:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: movi d1, #0xffff0000ffff0000
+; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b
+; NONEON-NOSVE-NEXT: ret
%c = and <4 x i16> %b, <i16 0, i16 65535, i16 0, i16 65535>
ret <4 x i16> %c
}
@@ -99,6 +138,12 @@ define <8 x i16> @vls_sve_and_8xi16(<8 x i16> %b) nounwind {
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: vls_sve_and_8xi16:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: movi v1.2d, #0xffff0000ffff0000
+; NONEON-NOSVE-NEXT: and v0.16b, v0.16b, v1.16b
+; NONEON-NOSVE-NEXT: ret
%c = and <8 x i16> %b, <i16 0, i16 65535, i16 0, i16 65535, i16 0, i16 65535, i16 0, i16 65535>
ret <8 x i16> %c
}
@@ -115,6 +160,13 @@ define <16 x i16> @vls_sve_and_16xi16(<16 x i16> %b) nounwind {
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: vls_sve_and_16xi16:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: movi v2.2d, #0xffff0000ffff0000
+; NONEON-NOSVE-NEXT: and v0.16b, v0.16b, v2.16b
+; NONEON-NOSVE-NEXT: and v1.16b, v1.16b, v2.16b
+; NONEON-NOSVE-NEXT: ret
%c = and <16 x i16> %b, <i16 0, i16 65535, i16 0, i16 65535, i16 0, i16 65535, i16 0, i16 65535, i16 0, i16 65535, i16 0, i16 65535, i16 0, i16 65535, i16 0, i16 65535>
ret <16 x i16> %c
}
@@ -128,6 +180,13 @@ define <2 x i32> @vls_sve_and_2xi32(<2 x i32> %b) nounwind {
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: vls_sve_and_2xi32:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0
+; NONEON-NOSVE-NEXT: mov v0.s[0], wzr
+; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0
+; NONEON-NOSVE-NEXT: ret
%c = and <2 x i32> %b, <i32 0, i32 4294967295>
ret <2 x i32> %c
}
@@ -141,6 +200,12 @@ define <4 x i32> @vls_sve_and_4xi32(<4 x i32> %b) nounwind {
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: vls_sve_and_4xi32:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: movi v1.2d, #0xffffffff00000000
+; NONEON-NOSVE-NEXT: and v0.16b, v0.16b, v1.16b
+; NONEON-NOSVE-NEXT: ret
%c = and <4 x i32> %b, <i32 0, i32 4294967295, i32 0, i32 4294967295>
ret <4 x i32> %c
}
@@ -157,6 +222,13 @@ define <8 x i32> @vls_sve_and_8xi32(<8 x i32> %b) nounwind {
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: vls_sve_and_8xi32:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: movi v2.2d, #0xffffffff00000000
+; NONEON-NOSVE-NEXT: and v0.16b, v0.16b, v2.16b
+; NONEON-NOSVE-NEXT: and v1.16b, v1.16b, v2.16b
+; NONEON-NOSVE-NEXT: ret
%c = and <8 x i32> %b, <i32 0, i32 4294967295, i32 0, i32 4294967295, i32 0, i32 4294967295, i32 0, i32 4294967295>
ret <8 x i32> %c
}
@@ -170,6 +242,11 @@ define <2 x i64> @vls_sve_and_2xi64(<2 x i64> %b) nounwind {
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: vls_sve_and_2xi64:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: mov v0.d[0], xzr
+; NONEON-NOSVE-NEXT: ret
%c = and <2 x i64> %b, <i64 0, i64 18446744073709551615>
ret <2 x i64> %c
}
@@ -185,6 +262,12 @@ define <4 x i64> @vls_sve_and_4xi64(<4 x i64> %b) nounwind {
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: vls_sve_and_4xi64:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: mov v0.d[0], xzr
+; NONEON-NOSVE-NEXT: mov v1.d[0], xzr
+; NONEON-NOSVE-NEXT: ret
%c = and <4 x i64> %b, <i64 0, i64 18446744073709551615, i64 0, i64 18446744073709551615>
ret <4 x i64> %c
}
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll
index d547f99a0230a6..8f0378252a54ef 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE
target triple = "aarch64-unknown-linux-gnu"
@@ -18,6 +19,16 @@ define <4 x i8> @ctlz_v4i8(<4 x i8> %op) {
; CHECK-NEXT: sub z0.h, z0.h, #8 // =0x8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: ctlz_v4i8:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: movi d1, #0xff00ff00ff00ff
+; NONEON-NOSVE-NEXT: mov w8, #8 // =0x8
+; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b
+; NONEON-NOSVE-NEXT: dup v1.4h, w8
+; NONEON-NOSVE-NEXT: clz v0.4h, v0.4h
+; NONEON-NOSVE-NEXT: sub v0.4h, v0.4h, v1.4h
+; NONEON-NOSVE-NEXT: ret
%res = call <4 x i8> @llvm.ctlz.v4i8(<4 x i8> %op)
ret <4 x i8> %res
}
@@ -30,6 +41,11 @@ define <8 x i8> @ctlz_v8i8(<8 x i8> %op) {
; CHECK-NEXT: clz z0.b, p0/m, z0.b
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: ctlz_v8i8:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: clz v0.8b, v0.8b
+; NONEON-NOSVE-NEXT: ret
%res = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %op)
ret <8 x i8> %res
}
@@ -42,6 +58,11 @@ define <16 x i8> @ctlz_v16i8(<16 x i8> %op) {
; CHECK-NEXT: clz z0.b, p0/m, z0.b
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: ctlz_v16i8:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: clz v0.16b, v0.16b
+; NONEON-NOSVE-NEXT: ret
%res = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %op)
ret <16 x i8> %res
}
@@ -55,6 +76,14 @@ define void @ctlz_v32i8(ptr %a) {
; CHECK-NEXT: clz z1.b, p0/m, z1.b
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: ctlz_v32i8:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
+; NONEON-NOSVE-NEXT: clz v0.16b, v0.16b
+; NONEON-NOSVE-NEXT: clz v1.16b, v1.16b
+; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
+; NONEON-NOSVE-NEXT: ret
%op = load <32 x i8>, ptr %a
%res = call <32 x i8> @llvm.ctlz.v32i8(<32 x i8> %op)
store <32 x i8> %res, ptr %a
@@ -71,6 +100,16 @@ define <2 x i16> @ctlz_v2i16(<2 x i16> %op) {
; CHECK-NEXT: sub z0.s, z0.s, #16 // =0x10
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: ctlz_v2i16:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: movi d1, #0x00ffff0000ffff
+; NONEON-NOSVE-NEXT: mov w8, #16 // =0x10
+; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b
+; NONEON-NOSVE-NEXT: dup v1.2s, w8
+; NONEON-NOSVE-NEXT: clz v0.2s, v0.2s
+; NONEON-NOSVE-NEXT: sub v0.2s, v0.2s, v1.2s
+; NONEON-NOSVE-NEXT: ret
%res = call <2 x i16> @llvm.ctlz.v2i16(<2 x i16> %op)
ret <2 x i16> %res
}
@@ -83,6 +122,11 @@ define <4 x i16> @ctlz_v4i16(<4 x i16> %op) {
; CHECK-NEXT: clz z0.h, p0/m, z0.h
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: ctlz_v4i16:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: clz v0.4h, v0.4h
+; NONEON-NOSVE-NEXT: ret
%res = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %op)
ret <4 x i16> %res
}
@@ -95,6 +139,11 @@ define <8 x i16> @ctlz_v8i16(<8 x i16> %op) {
; CHECK-NEXT: clz z0.h, p0/m, z0.h
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: ctlz_v8i16:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: clz v0.8h, v0.8h
+; NONEON-NOSVE-NEXT: ret
%res = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %op)
ret <8 x i16> %res
}
@@ -108,6 +157,14 @@ define void @ctlz_v16i16(ptr %a) {
; CHECK-NEXT: clz z1.h, p0/m, z1.h
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: ctlz_v16i16:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
+; NONEON-NOSVE-NEXT: clz v0.8h, v0.8h
+; NONEON-NOSVE-NEXT: clz v1.8h, v1.8h
+; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
+; NONEON-NOSVE-NEXT: ret
%op = load <16 x i16>, ptr %a
%res = call <16 x i16> @llvm.ctlz.v16i16(<16 x i16> %op)
store <16 x i16> %res, ptr %a
@@ -122,6 +179,11 @@ define <2 x i32> @ctlz_v2i32(<2 x i32> %op) {
; CHECK-NEXT: clz z0.s, p0/m, z0.s
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: ctlz_v2i32:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: clz v0.2s, v0.2s
+; NONEON-NOSVE-NEXT: ret
%res = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %op)
ret <2 x i32> %res
}
@@ -134,6 +196,11 @@ define <4 x i32> @ctlz_v4i32(<4 x i32> %op) {
; CHECK-NEXT: clz z0.s, p0/m, z0.s
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: ctlz_v4i32:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: clz v0.4s, v0.4s
+; NONEON-NOSVE-NEXT: ret
%res = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %op)
ret <4 x i32> %res
}
@@ -147,6 +214,14 @@ define void @ctlz_v8i32(ptr %a) {
; CHECK-NEXT: clz z1.s, p0/m, z1.s
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: ctlz_v8i32:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
+; NONEON-NOSVE-NEXT: clz v0.4s, v0.4s
+; NONEON-NOSVE-NEXT: clz v1.4s, v1.4s
+; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
+; NONEON-NOSVE-NEXT: ret
%op = load <8 x i32>, ptr %a
%res = call <8 x i32> @llvm.ctlz.v8i32(<8 x i32> %op)
store <8 x i32> %res, ptr %a
@@ -161,6 +236,27 @@ define <1 x i64> @ctlz_v1i64(<1 x i64> %op) {
; CHECK-NEXT: clz z0.d, p0/m, z0.d
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: ctlz_v1i64:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: ushr d1, d0, #1
+; NONEON-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b
+; NONEON-NOSVE-NEXT: ushr d1, d0, #2
+; NONEON-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b
+; NONEON-NOSVE-NEXT: ushr d1, d0, #4
+; NONEON-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b
+; NONEON-NOSVE-NEXT: ushr d1, d0, #8
+; NONEON-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b
+; NONEON-NOSVE-NEXT: ushr d1, d0, #16
+; NONEON-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b
+; NONEON-NOSVE-NEXT: ushr d1, d0, #32
+; NONEON-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b
+; NONEON-NOSVE-NEXT: mvn v0.8b, v0.8b
+; NONEON-NOSVE-NEXT: cnt v0.8b, v0.8b
+; NONEON-NOSVE-NEXT: uaddlp v0.4h, v0.8b
+; NONEON-NOSVE-NEXT: uaddlp v0.2s, v0.4h
+; NONEON-NOSVE-NEXT: uaddlp v0.1d, v0.2s
+; NONEON-NOSVE-NEXT: ret
%res = call <1 x i64> @llvm.ctlz.v1i64(<1 x i64> %op)
ret <1 x i64> %res
}
@@ -173,6 +269,27 @@ define <2 x i64> @ctlz_v2i64(<2 x i64> %op) {
; CHECK-NEXT: clz z0.d, p0/m, z0.d
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: ctlz_v2i64:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: ushr v1.2d, v0.2d, #1
+; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v1.16b
+; NONEON-NOSVE-NEXT: ushr v1.2d, v0.2d, #2
+; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v1.16b
+; NONEON-NOSVE-NEXT: ushr v1.2d, v0.2d, #4
+; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v1.16b
+; NONEON-NOSVE-NEXT: ushr v1.2d, v0.2d, #8
+; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v1.16b
+; NONEON-NOSVE-NEXT: ushr v1.2d, v0.2d, #16
+; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v1.16b
+; NONEON-NOSVE-NEXT: ushr v1.2d, v0.2d, #32
+; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v1.16b
+; NONEON-NOSVE-NEXT: mvn v0.16b, v0.16b
+; NONEON-NOSVE-NEXT: cnt v0.16b, v0.16b
+; NONEON-NOSVE-NEXT: uaddlp v0.8h, v0.16b
+; NONEON-NOSVE-NEXT: uaddlp v0.4s, v0.8h
+; NONEON-NOSVE-NEXT: uaddlp v0.2d, v0.4s
+; NONEON-NOSVE-NEXT: ret
%res = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %op)
ret <2 x i64> %res
}
@@ -186,6 +303,46 @@ define void @ctlz_v4i64(ptr %a) {
; CHECK-NEXT: clz z1.d, p0/m, z1.d
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: ctlz_v4i64:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
+; NONEON-NOSVE-NEXT: ushr v2.2d, v0.2d, #1
+; NONEON-NOSVE-NEXT: ushr v3.2d, v1.2d, #1
+; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v2.16b
+; NONEON-NOSVE-NEXT: orr v1.16b, v1.16b, v3.16b
+; NONEON-NOSVE-NEXT: ushr v2.2d, v0.2d, #2
+; NONEON-NOSVE-NEXT: ushr v3.2d, v1.2d, #2
+; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v2.16b
+; NONEON-NOSVE-NEXT: orr v1.16b, v1.16b, v3.16b
+; NONEON-NOSVE-NEXT: ushr v2.2d, v0.2d, #4
+; NONEON-NOSVE-NEXT: ushr v3.2d, v1.2d, #4
+; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v2.16b
+; NONEON-NOSVE-NEXT: orr v1.16b, v1.16b, v3.16b
+; NONEON-NOSVE-NEXT: ushr v2.2d, v0.2d, #8
+; NONEON-NOSVE-NEXT: ushr v3.2d, v1.2d, #8
+; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v2.16b
+; NONEON-NOSVE-NEXT: orr v1.16b, v1.16b, v3.16b
+; NONEON-NOSVE-NEXT: ushr v2.2d, v0.2d, #16
+; NONEON-NOSVE-NEXT: ushr v3.2d, v1.2d, #16
+; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v2.16b
+; NONEON-NOSVE-NEXT: orr v1.16b, v1.16b, v3.16b
+; NONEON-NOSVE-NEXT: ushr v2.2d, v0.2d, #32
+; NONEON-NOSVE-NEXT: ushr v3.2d, v1.2d, #32
+; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v2.16b
+; NONEON-NOSVE-NEXT: orr v1.16b, v1.16b, v3.16b
+; NONEON-NOSVE-NEXT: mvn v0.16b, v0.16b
+; NONEON-NOSVE-NEXT: mvn v1.16b, v1.16b
+; NONEON-NOSVE-NEXT: cnt v0.16b, v0.16b
+; NONEON-NOSVE-NEXT: cnt v1.16b, v1.16b
+; NONEON-NOSVE-NEXT: uaddlp v0.8h, v0.16b
+; NONEON-NOSVE-NEXT: uaddlp v1.8h, v1.16b
+; NONEON-NOSVE-NEXT: uaddlp v0.4s, v0.8h
+; NONEON-NOSVE-NEXT: uaddlp v1.4s, v1.8h
+; NONEON-NOSVE-NEXT: uaddlp v0.2d, v0.4s
+; NONEON-NOSVE-NEXT: uaddlp v1.2d, v1.4s
+; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
+; NONEON-NOSVE-NEXT: ret
%op = load <4 x i64>, ptr %a
%res = call <4 x i64> @llvm.ctlz.v4i64(<4 x i64> %op)
store <4 x i64> %res, ptr %a
@@ -205,6 +362,14 @@ define <4 x i8> @ctpop_v4i8(<4 x i8> %op) {
; CHECK-NEXT: cnt z0.h, p0/m, z0.h
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: ctpop_v4i8:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: movi d1, #0xff00ff00ff00ff
+; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b
+; NONEON-NOSVE-NEXT: cnt v0.8b, v0.8b
+; NONEON-NOSVE-NEXT: uaddlp v0.4h, v0.8b
+; NONEON-NOSVE-NEXT: ret
%res = call <4 x i8> @llvm.ctpop.v4i8(<4 x i8> %op)
ret <4 x i8> %res
}
@@ -217,6 +382,11 @@ define <8 x i8> @ctpop_v8i8(<8 x i8> %op) {
; CHECK-NEXT: cnt z0.b, p0/m, z0.b
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: ctpop_v8i8:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: cnt v0.8b, v0.8b
+; NONEON-NOSVE-NEXT: ret
%res = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %op)
ret <8 x i8> %res
}
@@ -229,6 +399,11 @@ define <16 x i8> @ctpop_v16i8(<16 x i8> %op) {
; CHECK-NEXT: cnt z0.b, p0/m, z0.b
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: ctpop_v16i8:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: cnt v0.16b, v0.16b
+; NONEON-NOSVE-NEXT: ret
%res = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %op)
ret <16 x i8> %res
}
@@ -242,6 +417,14 @@ define void @ctpop_v32i8(ptr %a) {
; CHECK-NEXT: cnt z1.b, p0/m, z1.b
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
+;
+; NONEON-NOSVE-LABEL: ctpop_v32i8:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
+; NONEON-NOSVE-NEXT: cnt v0.16b, v0.16b
+; NONEON-NOSVE-NEXT: cnt v1.16b, v1.16b
+; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
+; NONEON-NOSVE-NEXT: ret
%op = load <32 x i8>, ptr %a
%res = call <32 x i8> @llvm.ctpop.v32i8(<32 x i8> %op)
store <32 x i8> %res, ptr %a
@@ -257,6 +440,15 @@ define <2 x i16> @ctpop_v2i16(<2 x i16> %op) {
; CHECK-NEXT: cnt z0.s...
[truncated]
|
The intent is to test lowering of vector operations by scalarization, for functions that are streaming-compatible (and thus cannot use NEON) and also don't have the +sve attribute. The generated code is clearly wrong at the moment, but a series of patches will follow to fix up all cases to use scalar instructions. A bit of context: This work will form the base to decouple SME from SVE later on, as it will make sure that no NEON instructions are used in streaming[-compatible] mode. Later this will be followed by a patch that changes 'useSVEForFixedLengthVectors' to only return 'true' if SVE is available for the given runtime mode, at which point I'll change the `-mattr=+sme -force-streaming-compatible-sve` to `-mattr=+sme -force-streaming-sve`, so that the tests are considered to be executed in Streaming-SVE mode.
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The intent is to test lowering of vector operations by scalarization, for functions that are streaming-compatible (and thus cannot use NEON) and also don't have the +sve attribute.
The generated code is clearly wrong at the moment, but a series of patches will follow to fix up all cases to use scalar instructions.
A bit of context:
This work will form the base to decouple SME from SVE later on, as it will make sure that no NEON instructions are used in streaming[-compatible] mode. Later this will be followed by a patch that changes
useSVEForFixedLengthVectorsto only returntrueif SVE is available for the given runtime mode, at which point I'll change the-mattr=+sme -force-streaming-compatible-sveto-mattr=+sme -force-streaming-svein the RUN lines, so that the tests are considered to be executed in Streaming-SVE mode.