[Target] Use StringRef::operator== instead of StringRef::equals (NFC) (#91072) #91138
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…llvm#91072) I'm planning to remove StringRef::equals in favor of StringRef::operator==. - StringRef::operator==/!= outnumber StringRef::equals by a factor of 38 under llvm/ in terms of their usage. - The elimination of StringRef::equals brings StringRef closer to std::string_view, which has operator== but not equals. - S == "foo" is more readable than S.equals("foo"), especially for !Long.Expression.equals("str") vs Long.Expression != "str".
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@llvm/pr-subscribers-backend-powerpc @llvm/pr-subscribers-backend-aarch64 Author: Kazu Hirata (kazutakahirata) ChangesI'm planning to remove StringRef::equals in favor of
Full diff: https://github.com/llvm/llvm-project/pull/91138.diff 16 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
index 1a8c71888a852f..c3d64f5a0a9652 100644
--- a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
@@ -56,13 +56,13 @@ static std::pair<bool, bool> GetSignReturnAddress(const Function &F) {
}
StringRef Scope = F.getFnAttribute("sign-return-address").getValueAsString();
- if (Scope.equals("none"))
+ if (Scope == "none")
return {false, false};
- if (Scope.equals("all"))
+ if (Scope == "all")
return {true, true};
- assert(Scope.equals("non-leaf"));
+ assert(Scope == "non-leaf");
return {true, false};
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index c090d6133dbad4..89a5ceac629b16 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -1306,7 +1306,7 @@ void AMDGPUAsmPrinter::emitResourceUsageRemarks(
// makes it easier to tell which resource usage go with which kernel since
// the kernel name will always be displayed first.
std::string LabelStr = RemarkLabel.str() + ": ";
- if (!RemarkName.equals("FunctionName"))
+ if (RemarkName != "FunctionName")
LabelStr = Indent + LabelStr;
ORE->emit([&]() {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
index 9bd30458bc0a7e..43bfd0f13f875a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
@@ -332,9 +332,9 @@ struct AAUniformWorkGroupSizeFunction : public AAUniformWorkGroupSize {
bool InitialValue = false;
if (F->hasFnAttribute("uniform-work-group-size"))
- InitialValue = F->getFnAttribute("uniform-work-group-size")
- .getValueAsString()
- .equals("true");
+ InitialValue =
+ F->getFnAttribute("uniform-work-group-size").getValueAsString() ==
+ "true";
if (InitialValue)
indicateOptimisticFixpoint();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 3124fb23fb0be7..b95acdb3550b01 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -1460,7 +1460,7 @@ SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
if (G->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
G->getAddressSpace() == AMDGPUAS::REGION_ADDRESS) {
if (!MFI->isModuleEntryFunction() &&
- !GV->getName().equals("llvm.amdgcn.module.lds")) {
+ GV->getName() != "llvm.amdgcn.module.lds") {
SDLoc DL(Op);
const Function &Fn = DAG.getMachineFunction().getFunction();
DiagnosticInfoUnsupported BadLDSDecl(
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 6cd93abff1a429..bd7bf78c4c0bdc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -2919,7 +2919,7 @@ bool AMDGPULegalizerInfo::legalizeGlobalValue(
if (AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::REGION_ADDRESS) {
if (!MFI->isModuleEntryFunction() &&
- !GV->getName().equals("llvm.amdgcn.module.lds")) {
+ GV->getName() != "llvm.amdgcn.module.lds") {
const Function &Fn = MF.getFunction();
DiagnosticInfoUnsupported BadLDSDecl(
Fn, "local memory global used by non-kernel function", MI.getDebugLoc(),
diff --git a/llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp b/llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp
index a364992fab3ed5..54207562dbaeba 100644
--- a/llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp
@@ -61,13 +61,13 @@ static std::pair<bool, bool> GetSignReturnAddress(const Function &F) {
}
StringRef Scope = F.getFnAttribute("sign-return-address").getValueAsString();
- if (Scope.equals("none"))
+ if (Scope == "none")
return {false, false};
- if (Scope.equals("all"))
+ if (Scope == "all")
return {true, true};
- assert(Scope.equals("non-leaf"));
+ assert(Scope == "non-leaf");
return {true, false};
}
diff --git a/llvm/lib/Target/BPF/BTFDebug.cpp b/llvm/lib/Target/BPF/BTFDebug.cpp
index 8c9f5c4dc55487..b6d3b460005c94 100644
--- a/llvm/lib/Target/BPF/BTFDebug.cpp
+++ b/llvm/lib/Target/BPF/BTFDebug.cpp
@@ -588,7 +588,7 @@ void BTFDebug::processDeclAnnotations(DINodeArray Annotations,
for (const Metadata *Annotation : Annotations->operands()) {
const MDNode *MD = cast<MDNode>(Annotation);
const MDString *Name = cast<MDString>(MD->getOperand(0));
- if (!Name->getString().equals("btf_decl_tag"))
+ if (Name->getString() != "btf_decl_tag")
continue;
const MDString *Value = cast<MDString>(MD->getOperand(1));
@@ -627,7 +627,7 @@ int BTFDebug::genBTFTypeTags(const DIDerivedType *DTy, int BaseTypeId) {
for (const Metadata *Annotations : Annots->operands()) {
const MDNode *MD = cast<MDNode>(Annotations);
const MDString *Name = cast<MDString>(MD->getOperand(0));
- if (!Name->getString().equals("btf_type_tag"))
+ if (Name->getString() != "btf_type_tag")
continue;
MDStrs.push_back(cast<MDString>(MD->getOperand(1)));
}
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp b/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
index a7ac24e25a5fef..35188ff2e97f46 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
@@ -86,7 +86,7 @@ static cl::opt<bool>
static bool isSmallDataSection(StringRef Sec) {
// sectionName is either ".sdata" or ".sbss". Looking for an exact match
// obviates the need for checks for section names such as ".sdatafoo".
- if (Sec.equals(".sdata") || Sec.equals(".sbss") || Sec.equals(".scommon"))
+ if (Sec == ".sdata" || Sec == ".sbss" || Sec == ".scommon")
return true;
// If either ".sdata." or ".sbss." is a substring of the section name
// then put the symbol in small data.
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
index 0a948402fb896a..eab7647e633bcc 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
@@ -158,7 +158,7 @@ StringRef Hexagon_MC::selectHexagonCPU(StringRef CPU) {
// non-tiny subtarget. See: addArchSubtarget
std::pair<StringRef, StringRef> ArchP = ArchV.split('t');
std::pair<StringRef, StringRef> CPUP = CPU.split('t');
- if (!ArchP.first.equals(CPUP.first))
+ if (ArchP.first != CPUP.first)
report_fatal_error("conflicting architectures specified.");
return CPU;
}
@@ -578,7 +578,7 @@ MCSubtargetInfo *Hexagon_MC::createHexagonMCSubtargetInfo(const Triple &TT,
if (X != nullptr && (CPUName == "hexagonv67t" || CPUName == "hexagon71t"))
addArchSubtarget(X, ArchFS);
- if (CPU.equals("help"))
+ if (CPU == "help")
exit(0);
if (!isCPUValid(CPUName.str())) {
diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
index 51b79dc2b04b4e..405326f4530a19 100644
--- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -2896,7 +2896,7 @@ void PPCAIXAsmPrinter::emitPGORefs(Module &M) {
bool HasNonZeroLengthPrfCntsSection = false;
const DataLayout &DL = M.getDataLayout();
for (GlobalVariable &GV : M.globals())
- if (GV.hasSection() && GV.getSection().equals("__llvm_prf_cnts") &&
+ if (GV.hasSection() && GV.getSection() == "__llvm_prf_cnts" &&
DL.getTypeAllocSize(GV.getValueType()) > 0) {
HasNonZeroLengthPrfCntsSection = true;
break;
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 36f77488d91409..48ee8b5d8d817d 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -5302,9 +5302,10 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
SDValue MDV = N->getOperand(MDIndex);
const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
assert(MD->getNumOperands() != 0 && "Empty MDNode in operands!");
- assert((isa<MDString>(MD->getOperand(0)) && cast<MDString>(
- MD->getOperand(0))->getString().equals("ppc-trap-reason"))
- && "Unsupported annotation data type!");
+ assert((isa<MDString>(MD->getOperand(0)) &&
+ cast<MDString>(MD->getOperand(0))->getString() ==
+ "ppc-trap-reason") &&
+ "Unsupported annotation data type!");
for (unsigned i = 1; i < MD->getNumOperands(); i++) {
assert(isa<MDString>(MD->getOperand(i)) &&
"Invalid data type for annotation ppc-trap-reason!");
diff --git a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
index a182be3ea712b4..d45edd74ab8544 100644
--- a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
@@ -415,7 +415,7 @@ static bool hasPCRelativeForm(MachineInstr &Use) {
bool runOnMachineFunction(MachineFunction &MF) override {
// If the user wants to set the DSCR using command-line options,
// load in the specified value at the start of main.
- if (DSCRValue.getNumOccurrences() > 0 && MF.getName().equals("main") &&
+ if (DSCRValue.getNumOccurrences() > 0 && MF.getName() == "main" &&
MF.getFunction().hasExternalLinkage()) {
DSCRValue = (uint32_t)(DSCRValue & 0x01FFFFFF); // 25-bit DSCR mask
RegScavenger RS;
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 7439d0fefa9800..32de8b9587b46f 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -1763,7 +1763,7 @@ static bool buildNDRange(const SPIRV::IncomingCall *Call,
if (!MRI->getRegClassOrNull(GWSPtr))
MRI->setRegClass(GWSPtr, &SPIRV::IDRegClass);
// TODO: Maybe simplify generation of the type of the fields.
- unsigned Size = Call->Builtin->Name.equals("ndrange_3D") ? 3 : 2;
+ unsigned Size = Call->Builtin->Name == "ndrange_3D" ? 3 : 2;
unsigned BitWidth = GR->getPointerSize() == 64 ? 64 : 32;
Type *BaseTy = IntegerType::get(MF.getFunction().getContext(), BitWidth);
Type *FieldTy = ArrayType::get(BaseTy, Size);
diff --git a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
index 67e2b9d7c99782..185b2fe90c6cb6 100644
--- a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
+++ b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
@@ -1377,7 +1377,7 @@ MCRegister SparcAsmParser::matchRegisterName(const AsmToken &Tok,
return IntRegs[RegNo];
}
- if (Name.equals("xcc")) {
+ if (Name == "xcc") {
// FIXME:: check 64bit.
RegKind = SparcOperand::rk_Special;
return SP::ICC;
@@ -1385,36 +1385,36 @@ MCRegister SparcAsmParser::matchRegisterName(const AsmToken &Tok,
// JPS1 extension - aliases for ASRs
// Section A.51 - Read State Register
- if (Name.equals("pcr")) {
+ if (Name == "pcr") {
RegKind = SparcOperand::rk_Special;
return SP::ASR16;
}
- if (Name.equals("pic")) {
+ if (Name == "pic") {
RegKind = SparcOperand::rk_Special;
return SP::ASR17;
}
- if (Name.equals("dcr")) {
+ if (Name == "dcr") {
RegKind = SparcOperand::rk_Special;
return SP::ASR18;
}
- if (Name.equals("gsr")) {
+ if (Name == "gsr") {
RegKind = SparcOperand::rk_Special;
return SP::ASR19;
}
- if (Name.equals("softint")) {
+ if (Name == "softint") {
RegKind = SparcOperand::rk_Special;
return SP::ASR22;
}
- if (Name.equals("tick_cmpr")) {
+ if (Name == "tick_cmpr") {
RegKind = SparcOperand::rk_Special;
return SP::ASR23;
}
- if (Name.equals("stick") || Name.equals("sys_tick")) {
+ if (Name == "stick" || Name == "sys_tick") {
RegKind = SparcOperand::rk_Special;
return SP::ASR24;
}
- if (Name.equals("stick_cmpr") || Name.equals("sys_tick_cmpr")) {
+ if (Name == "stick_cmpr" || Name == "sys_tick_cmpr") {
RegKind = SparcOperand::rk_Special;
return SP::ASR25;
}
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 2c2dc21f191d7a..62b4a9278954ce 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -2296,7 +2296,7 @@ bool X86AsmParser::ParseRoundingModeOp(SMLoc Start, OperandVector &Operands) {
Operands.push_back(X86Operand::CreateImm(RndModeOp, Start, End));
return false;
}
- if(Tok.getIdentifier().equals("sae")){
+ if (Tok.getIdentifier() == "sae") {
Parser.Lex(); // Eat the sae
if (!getLexer().is(AsmToken::RCurly))
return Error(Tok.getLoc(), "Expected } at this point");
@@ -2567,7 +2567,7 @@ bool X86AsmParser::ParseIntelMemoryOperandSize(unsigned &Size) {
.Default(0);
if (Size) {
const AsmToken &Tok = Lex(); // Eat operand size (e.g., byte, word).
- if (!(Tok.getString().equals("PTR") || Tok.getString().equals("ptr")))
+ if (!(Tok.getString() == "PTR" || Tok.getString() == "ptr"))
return Error(Tok.getLoc(), "Expected 'PTR' or 'ptr' token!");
Lex(); // Eat ptr.
}
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 3d80c43b571f9c..0e5e52d4d88e85 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -3570,7 +3570,7 @@ bool X86InstrInfo::canMakeTailCallConditional(
if (Target.isSymbol()) {
StringRef Symbol(Target.getSymbolName());
// this is currently only relevant to r11/kernel indirect thunk.
- if (Symbol.equals("__x86_indirect_thunk_r11"))
+ if (Symbol == "__x86_indirect_thunk_r11")
return false;
}
}
|
|
@llvm/pr-subscribers-backend-sparc Author: Kazu Hirata (kazutakahirata) ChangesI'm planning to remove StringRef::equals in favor of
Full diff: https://github.com/llvm/llvm-project/pull/91138.diff 16 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
index 1a8c71888a852f..c3d64f5a0a9652 100644
--- a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
@@ -56,13 +56,13 @@ static std::pair<bool, bool> GetSignReturnAddress(const Function &F) {
}
StringRef Scope = F.getFnAttribute("sign-return-address").getValueAsString();
- if (Scope.equals("none"))
+ if (Scope == "none")
return {false, false};
- if (Scope.equals("all"))
+ if (Scope == "all")
return {true, true};
- assert(Scope.equals("non-leaf"));
+ assert(Scope == "non-leaf");
return {true, false};
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index c090d6133dbad4..89a5ceac629b16 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -1306,7 +1306,7 @@ void AMDGPUAsmPrinter::emitResourceUsageRemarks(
// makes it easier to tell which resource usage go with which kernel since
// the kernel name will always be displayed first.
std::string LabelStr = RemarkLabel.str() + ": ";
- if (!RemarkName.equals("FunctionName"))
+ if (RemarkName != "FunctionName")
LabelStr = Indent + LabelStr;
ORE->emit([&]() {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
index 9bd30458bc0a7e..43bfd0f13f875a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
@@ -332,9 +332,9 @@ struct AAUniformWorkGroupSizeFunction : public AAUniformWorkGroupSize {
bool InitialValue = false;
if (F->hasFnAttribute("uniform-work-group-size"))
- InitialValue = F->getFnAttribute("uniform-work-group-size")
- .getValueAsString()
- .equals("true");
+ InitialValue =
+ F->getFnAttribute("uniform-work-group-size").getValueAsString() ==
+ "true";
if (InitialValue)
indicateOptimisticFixpoint();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 3124fb23fb0be7..b95acdb3550b01 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -1460,7 +1460,7 @@ SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
if (G->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
G->getAddressSpace() == AMDGPUAS::REGION_ADDRESS) {
if (!MFI->isModuleEntryFunction() &&
- !GV->getName().equals("llvm.amdgcn.module.lds")) {
+ GV->getName() != "llvm.amdgcn.module.lds") {
SDLoc DL(Op);
const Function &Fn = DAG.getMachineFunction().getFunction();
DiagnosticInfoUnsupported BadLDSDecl(
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 6cd93abff1a429..bd7bf78c4c0bdc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -2919,7 +2919,7 @@ bool AMDGPULegalizerInfo::legalizeGlobalValue(
if (AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::REGION_ADDRESS) {
if (!MFI->isModuleEntryFunction() &&
- !GV->getName().equals("llvm.amdgcn.module.lds")) {
+ GV->getName() != "llvm.amdgcn.module.lds") {
const Function &Fn = MF.getFunction();
DiagnosticInfoUnsupported BadLDSDecl(
Fn, "local memory global used by non-kernel function", MI.getDebugLoc(),
diff --git a/llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp b/llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp
index a364992fab3ed5..54207562dbaeba 100644
--- a/llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp
@@ -61,13 +61,13 @@ static std::pair<bool, bool> GetSignReturnAddress(const Function &F) {
}
StringRef Scope = F.getFnAttribute("sign-return-address").getValueAsString();
- if (Scope.equals("none"))
+ if (Scope == "none")
return {false, false};
- if (Scope.equals("all"))
+ if (Scope == "all")
return {true, true};
- assert(Scope.equals("non-leaf"));
+ assert(Scope == "non-leaf");
return {true, false};
}
diff --git a/llvm/lib/Target/BPF/BTFDebug.cpp b/llvm/lib/Target/BPF/BTFDebug.cpp
index 8c9f5c4dc55487..b6d3b460005c94 100644
--- a/llvm/lib/Target/BPF/BTFDebug.cpp
+++ b/llvm/lib/Target/BPF/BTFDebug.cpp
@@ -588,7 +588,7 @@ void BTFDebug::processDeclAnnotations(DINodeArray Annotations,
for (const Metadata *Annotation : Annotations->operands()) {
const MDNode *MD = cast<MDNode>(Annotation);
const MDString *Name = cast<MDString>(MD->getOperand(0));
- if (!Name->getString().equals("btf_decl_tag"))
+ if (Name->getString() != "btf_decl_tag")
continue;
const MDString *Value = cast<MDString>(MD->getOperand(1));
@@ -627,7 +627,7 @@ int BTFDebug::genBTFTypeTags(const DIDerivedType *DTy, int BaseTypeId) {
for (const Metadata *Annotations : Annots->operands()) {
const MDNode *MD = cast<MDNode>(Annotations);
const MDString *Name = cast<MDString>(MD->getOperand(0));
- if (!Name->getString().equals("btf_type_tag"))
+ if (Name->getString() != "btf_type_tag")
continue;
MDStrs.push_back(cast<MDString>(MD->getOperand(1)));
}
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp b/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
index a7ac24e25a5fef..35188ff2e97f46 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
@@ -86,7 +86,7 @@ static cl::opt<bool>
static bool isSmallDataSection(StringRef Sec) {
// sectionName is either ".sdata" or ".sbss". Looking for an exact match
// obviates the need for checks for section names such as ".sdatafoo".
- if (Sec.equals(".sdata") || Sec.equals(".sbss") || Sec.equals(".scommon"))
+ if (Sec == ".sdata" || Sec == ".sbss" || Sec == ".scommon")
return true;
// If either ".sdata." or ".sbss." is a substring of the section name
// then put the symbol in small data.
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
index 0a948402fb896a..eab7647e633bcc 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
@@ -158,7 +158,7 @@ StringRef Hexagon_MC::selectHexagonCPU(StringRef CPU) {
// non-tiny subtarget. See: addArchSubtarget
std::pair<StringRef, StringRef> ArchP = ArchV.split('t');
std::pair<StringRef, StringRef> CPUP = CPU.split('t');
- if (!ArchP.first.equals(CPUP.first))
+ if (ArchP.first != CPUP.first)
report_fatal_error("conflicting architectures specified.");
return CPU;
}
@@ -578,7 +578,7 @@ MCSubtargetInfo *Hexagon_MC::createHexagonMCSubtargetInfo(const Triple &TT,
if (X != nullptr && (CPUName == "hexagonv67t" || CPUName == "hexagon71t"))
addArchSubtarget(X, ArchFS);
- if (CPU.equals("help"))
+ if (CPU == "help")
exit(0);
if (!isCPUValid(CPUName.str())) {
diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
index 51b79dc2b04b4e..405326f4530a19 100644
--- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -2896,7 +2896,7 @@ void PPCAIXAsmPrinter::emitPGORefs(Module &M) {
bool HasNonZeroLengthPrfCntsSection = false;
const DataLayout &DL = M.getDataLayout();
for (GlobalVariable &GV : M.globals())
- if (GV.hasSection() && GV.getSection().equals("__llvm_prf_cnts") &&
+ if (GV.hasSection() && GV.getSection() == "__llvm_prf_cnts" &&
DL.getTypeAllocSize(GV.getValueType()) > 0) {
HasNonZeroLengthPrfCntsSection = true;
break;
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 36f77488d91409..48ee8b5d8d817d 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -5302,9 +5302,10 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
SDValue MDV = N->getOperand(MDIndex);
const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
assert(MD->getNumOperands() != 0 && "Empty MDNode in operands!");
- assert((isa<MDString>(MD->getOperand(0)) && cast<MDString>(
- MD->getOperand(0))->getString().equals("ppc-trap-reason"))
- && "Unsupported annotation data type!");
+ assert((isa<MDString>(MD->getOperand(0)) &&
+ cast<MDString>(MD->getOperand(0))->getString() ==
+ "ppc-trap-reason") &&
+ "Unsupported annotation data type!");
for (unsigned i = 1; i < MD->getNumOperands(); i++) {
assert(isa<MDString>(MD->getOperand(i)) &&
"Invalid data type for annotation ppc-trap-reason!");
diff --git a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
index a182be3ea712b4..d45edd74ab8544 100644
--- a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
@@ -415,7 +415,7 @@ static bool hasPCRelativeForm(MachineInstr &Use) {
bool runOnMachineFunction(MachineFunction &MF) override {
// If the user wants to set the DSCR using command-line options,
// load in the specified value at the start of main.
- if (DSCRValue.getNumOccurrences() > 0 && MF.getName().equals("main") &&
+ if (DSCRValue.getNumOccurrences() > 0 && MF.getName() == "main" &&
MF.getFunction().hasExternalLinkage()) {
DSCRValue = (uint32_t)(DSCRValue & 0x01FFFFFF); // 25-bit DSCR mask
RegScavenger RS;
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 7439d0fefa9800..32de8b9587b46f 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -1763,7 +1763,7 @@ static bool buildNDRange(const SPIRV::IncomingCall *Call,
if (!MRI->getRegClassOrNull(GWSPtr))
MRI->setRegClass(GWSPtr, &SPIRV::IDRegClass);
// TODO: Maybe simplify generation of the type of the fields.
- unsigned Size = Call->Builtin->Name.equals("ndrange_3D") ? 3 : 2;
+ unsigned Size = Call->Builtin->Name == "ndrange_3D" ? 3 : 2;
unsigned BitWidth = GR->getPointerSize() == 64 ? 64 : 32;
Type *BaseTy = IntegerType::get(MF.getFunction().getContext(), BitWidth);
Type *FieldTy = ArrayType::get(BaseTy, Size);
diff --git a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
index 67e2b9d7c99782..185b2fe90c6cb6 100644
--- a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
+++ b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
@@ -1377,7 +1377,7 @@ MCRegister SparcAsmParser::matchRegisterName(const AsmToken &Tok,
return IntRegs[RegNo];
}
- if (Name.equals("xcc")) {
+ if (Name == "xcc") {
// FIXME:: check 64bit.
RegKind = SparcOperand::rk_Special;
return SP::ICC;
@@ -1385,36 +1385,36 @@ MCRegister SparcAsmParser::matchRegisterName(const AsmToken &Tok,
// JPS1 extension - aliases for ASRs
// Section A.51 - Read State Register
- if (Name.equals("pcr")) {
+ if (Name == "pcr") {
RegKind = SparcOperand::rk_Special;
return SP::ASR16;
}
- if (Name.equals("pic")) {
+ if (Name == "pic") {
RegKind = SparcOperand::rk_Special;
return SP::ASR17;
}
- if (Name.equals("dcr")) {
+ if (Name == "dcr") {
RegKind = SparcOperand::rk_Special;
return SP::ASR18;
}
- if (Name.equals("gsr")) {
+ if (Name == "gsr") {
RegKind = SparcOperand::rk_Special;
return SP::ASR19;
}
- if (Name.equals("softint")) {
+ if (Name == "softint") {
RegKind = SparcOperand::rk_Special;
return SP::ASR22;
}
- if (Name.equals("tick_cmpr")) {
+ if (Name == "tick_cmpr") {
RegKind = SparcOperand::rk_Special;
return SP::ASR23;
}
- if (Name.equals("stick") || Name.equals("sys_tick")) {
+ if (Name == "stick" || Name == "sys_tick") {
RegKind = SparcOperand::rk_Special;
return SP::ASR24;
}
- if (Name.equals("stick_cmpr") || Name.equals("sys_tick_cmpr")) {
+ if (Name == "stick_cmpr" || Name == "sys_tick_cmpr") {
RegKind = SparcOperand::rk_Special;
return SP::ASR25;
}
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 2c2dc21f191d7a..62b4a9278954ce 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -2296,7 +2296,7 @@ bool X86AsmParser::ParseRoundingModeOp(SMLoc Start, OperandVector &Operands) {
Operands.push_back(X86Operand::CreateImm(RndModeOp, Start, End));
return false;
}
- if(Tok.getIdentifier().equals("sae")){
+ if (Tok.getIdentifier() == "sae") {
Parser.Lex(); // Eat the sae
if (!getLexer().is(AsmToken::RCurly))
return Error(Tok.getLoc(), "Expected } at this point");
@@ -2567,7 +2567,7 @@ bool X86AsmParser::ParseIntelMemoryOperandSize(unsigned &Size) {
.Default(0);
if (Size) {
const AsmToken &Tok = Lex(); // Eat operand size (e.g., byte, word).
- if (!(Tok.getString().equals("PTR") || Tok.getString().equals("ptr")))
+ if (!(Tok.getString() == "PTR" || Tok.getString() == "ptr"))
return Error(Tok.getLoc(), "Expected 'PTR' or 'ptr' token!");
Lex(); // Eat ptr.
}
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 3d80c43b571f9c..0e5e52d4d88e85 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -3570,7 +3570,7 @@ bool X86InstrInfo::canMakeTailCallConditional(
if (Target.isSymbol()) {
StringRef Symbol(Target.getSymbolName());
// this is currently only relevant to r11/kernel indirect thunk.
- if (Symbol.equals("__x86_indirect_thunk_r11"))
+ if (Symbol == "__x86_indirect_thunk_r11")
return false;
}
}
|
|
@llvm/pr-subscribers-backend-x86 Author: Kazu Hirata (kazutakahirata) ChangesI'm planning to remove StringRef::equals in favor of
Full diff: https://github.com/llvm/llvm-project/pull/91138.diff 16 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
index 1a8c71888a852f..c3d64f5a0a9652 100644
--- a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
@@ -56,13 +56,13 @@ static std::pair<bool, bool> GetSignReturnAddress(const Function &F) {
}
StringRef Scope = F.getFnAttribute("sign-return-address").getValueAsString();
- if (Scope.equals("none"))
+ if (Scope == "none")
return {false, false};
- if (Scope.equals("all"))
+ if (Scope == "all")
return {true, true};
- assert(Scope.equals("non-leaf"));
+ assert(Scope == "non-leaf");
return {true, false};
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index c090d6133dbad4..89a5ceac629b16 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -1306,7 +1306,7 @@ void AMDGPUAsmPrinter::emitResourceUsageRemarks(
// makes it easier to tell which resource usage go with which kernel since
// the kernel name will always be displayed first.
std::string LabelStr = RemarkLabel.str() + ": ";
- if (!RemarkName.equals("FunctionName"))
+ if (RemarkName != "FunctionName")
LabelStr = Indent + LabelStr;
ORE->emit([&]() {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
index 9bd30458bc0a7e..43bfd0f13f875a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
@@ -332,9 +332,9 @@ struct AAUniformWorkGroupSizeFunction : public AAUniformWorkGroupSize {
bool InitialValue = false;
if (F->hasFnAttribute("uniform-work-group-size"))
- InitialValue = F->getFnAttribute("uniform-work-group-size")
- .getValueAsString()
- .equals("true");
+ InitialValue =
+ F->getFnAttribute("uniform-work-group-size").getValueAsString() ==
+ "true";
if (InitialValue)
indicateOptimisticFixpoint();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 3124fb23fb0be7..b95acdb3550b01 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -1460,7 +1460,7 @@ SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
if (G->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
G->getAddressSpace() == AMDGPUAS::REGION_ADDRESS) {
if (!MFI->isModuleEntryFunction() &&
- !GV->getName().equals("llvm.amdgcn.module.lds")) {
+ GV->getName() != "llvm.amdgcn.module.lds") {
SDLoc DL(Op);
const Function &Fn = DAG.getMachineFunction().getFunction();
DiagnosticInfoUnsupported BadLDSDecl(
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 6cd93abff1a429..bd7bf78c4c0bdc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -2919,7 +2919,7 @@ bool AMDGPULegalizerInfo::legalizeGlobalValue(
if (AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::REGION_ADDRESS) {
if (!MFI->isModuleEntryFunction() &&
- !GV->getName().equals("llvm.amdgcn.module.lds")) {
+ GV->getName() != "llvm.amdgcn.module.lds") {
const Function &Fn = MF.getFunction();
DiagnosticInfoUnsupported BadLDSDecl(
Fn, "local memory global used by non-kernel function", MI.getDebugLoc(),
diff --git a/llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp b/llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp
index a364992fab3ed5..54207562dbaeba 100644
--- a/llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp
@@ -61,13 +61,13 @@ static std::pair<bool, bool> GetSignReturnAddress(const Function &F) {
}
StringRef Scope = F.getFnAttribute("sign-return-address").getValueAsString();
- if (Scope.equals("none"))
+ if (Scope == "none")
return {false, false};
- if (Scope.equals("all"))
+ if (Scope == "all")
return {true, true};
- assert(Scope.equals("non-leaf"));
+ assert(Scope == "non-leaf");
return {true, false};
}
diff --git a/llvm/lib/Target/BPF/BTFDebug.cpp b/llvm/lib/Target/BPF/BTFDebug.cpp
index 8c9f5c4dc55487..b6d3b460005c94 100644
--- a/llvm/lib/Target/BPF/BTFDebug.cpp
+++ b/llvm/lib/Target/BPF/BTFDebug.cpp
@@ -588,7 +588,7 @@ void BTFDebug::processDeclAnnotations(DINodeArray Annotations,
for (const Metadata *Annotation : Annotations->operands()) {
const MDNode *MD = cast<MDNode>(Annotation);
const MDString *Name = cast<MDString>(MD->getOperand(0));
- if (!Name->getString().equals("btf_decl_tag"))
+ if (Name->getString() != "btf_decl_tag")
continue;
const MDString *Value = cast<MDString>(MD->getOperand(1));
@@ -627,7 +627,7 @@ int BTFDebug::genBTFTypeTags(const DIDerivedType *DTy, int BaseTypeId) {
for (const Metadata *Annotations : Annots->operands()) {
const MDNode *MD = cast<MDNode>(Annotations);
const MDString *Name = cast<MDString>(MD->getOperand(0));
- if (!Name->getString().equals("btf_type_tag"))
+ if (Name->getString() != "btf_type_tag")
continue;
MDStrs.push_back(cast<MDString>(MD->getOperand(1)));
}
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp b/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
index a7ac24e25a5fef..35188ff2e97f46 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
@@ -86,7 +86,7 @@ static cl::opt<bool>
static bool isSmallDataSection(StringRef Sec) {
// sectionName is either ".sdata" or ".sbss". Looking for an exact match
// obviates the need for checks for section names such as ".sdatafoo".
- if (Sec.equals(".sdata") || Sec.equals(".sbss") || Sec.equals(".scommon"))
+ if (Sec == ".sdata" || Sec == ".sbss" || Sec == ".scommon")
return true;
// If either ".sdata." or ".sbss." is a substring of the section name
// then put the symbol in small data.
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
index 0a948402fb896a..eab7647e633bcc 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
@@ -158,7 +158,7 @@ StringRef Hexagon_MC::selectHexagonCPU(StringRef CPU) {
// non-tiny subtarget. See: addArchSubtarget
std::pair<StringRef, StringRef> ArchP = ArchV.split('t');
std::pair<StringRef, StringRef> CPUP = CPU.split('t');
- if (!ArchP.first.equals(CPUP.first))
+ if (ArchP.first != CPUP.first)
report_fatal_error("conflicting architectures specified.");
return CPU;
}
@@ -578,7 +578,7 @@ MCSubtargetInfo *Hexagon_MC::createHexagonMCSubtargetInfo(const Triple &TT,
if (X != nullptr && (CPUName == "hexagonv67t" || CPUName == "hexagon71t"))
addArchSubtarget(X, ArchFS);
- if (CPU.equals("help"))
+ if (CPU == "help")
exit(0);
if (!isCPUValid(CPUName.str())) {
diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
index 51b79dc2b04b4e..405326f4530a19 100644
--- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -2896,7 +2896,7 @@ void PPCAIXAsmPrinter::emitPGORefs(Module &M) {
bool HasNonZeroLengthPrfCntsSection = false;
const DataLayout &DL = M.getDataLayout();
for (GlobalVariable &GV : M.globals())
- if (GV.hasSection() && GV.getSection().equals("__llvm_prf_cnts") &&
+ if (GV.hasSection() && GV.getSection() == "__llvm_prf_cnts" &&
DL.getTypeAllocSize(GV.getValueType()) > 0) {
HasNonZeroLengthPrfCntsSection = true;
break;
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 36f77488d91409..48ee8b5d8d817d 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -5302,9 +5302,10 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
SDValue MDV = N->getOperand(MDIndex);
const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
assert(MD->getNumOperands() != 0 && "Empty MDNode in operands!");
- assert((isa<MDString>(MD->getOperand(0)) && cast<MDString>(
- MD->getOperand(0))->getString().equals("ppc-trap-reason"))
- && "Unsupported annotation data type!");
+ assert((isa<MDString>(MD->getOperand(0)) &&
+ cast<MDString>(MD->getOperand(0))->getString() ==
+ "ppc-trap-reason") &&
+ "Unsupported annotation data type!");
for (unsigned i = 1; i < MD->getNumOperands(); i++) {
assert(isa<MDString>(MD->getOperand(i)) &&
"Invalid data type for annotation ppc-trap-reason!");
diff --git a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
index a182be3ea712b4..d45edd74ab8544 100644
--- a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
@@ -415,7 +415,7 @@ static bool hasPCRelativeForm(MachineInstr &Use) {
bool runOnMachineFunction(MachineFunction &MF) override {
// If the user wants to set the DSCR using command-line options,
// load in the specified value at the start of main.
- if (DSCRValue.getNumOccurrences() > 0 && MF.getName().equals("main") &&
+ if (DSCRValue.getNumOccurrences() > 0 && MF.getName() == "main" &&
MF.getFunction().hasExternalLinkage()) {
DSCRValue = (uint32_t)(DSCRValue & 0x01FFFFFF); // 25-bit DSCR mask
RegScavenger RS;
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 7439d0fefa9800..32de8b9587b46f 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -1763,7 +1763,7 @@ static bool buildNDRange(const SPIRV::IncomingCall *Call,
if (!MRI->getRegClassOrNull(GWSPtr))
MRI->setRegClass(GWSPtr, &SPIRV::IDRegClass);
// TODO: Maybe simplify generation of the type of the fields.
- unsigned Size = Call->Builtin->Name.equals("ndrange_3D") ? 3 : 2;
+ unsigned Size = Call->Builtin->Name == "ndrange_3D" ? 3 : 2;
unsigned BitWidth = GR->getPointerSize() == 64 ? 64 : 32;
Type *BaseTy = IntegerType::get(MF.getFunction().getContext(), BitWidth);
Type *FieldTy = ArrayType::get(BaseTy, Size);
diff --git a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
index 67e2b9d7c99782..185b2fe90c6cb6 100644
--- a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
+++ b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
@@ -1377,7 +1377,7 @@ MCRegister SparcAsmParser::matchRegisterName(const AsmToken &Tok,
return IntRegs[RegNo];
}
- if (Name.equals("xcc")) {
+ if (Name == "xcc") {
// FIXME:: check 64bit.
RegKind = SparcOperand::rk_Special;
return SP::ICC;
@@ -1385,36 +1385,36 @@ MCRegister SparcAsmParser::matchRegisterName(const AsmToken &Tok,
// JPS1 extension - aliases for ASRs
// Section A.51 - Read State Register
- if (Name.equals("pcr")) {
+ if (Name == "pcr") {
RegKind = SparcOperand::rk_Special;
return SP::ASR16;
}
- if (Name.equals("pic")) {
+ if (Name == "pic") {
RegKind = SparcOperand::rk_Special;
return SP::ASR17;
}
- if (Name.equals("dcr")) {
+ if (Name == "dcr") {
RegKind = SparcOperand::rk_Special;
return SP::ASR18;
}
- if (Name.equals("gsr")) {
+ if (Name == "gsr") {
RegKind = SparcOperand::rk_Special;
return SP::ASR19;
}
- if (Name.equals("softint")) {
+ if (Name == "softint") {
RegKind = SparcOperand::rk_Special;
return SP::ASR22;
}
- if (Name.equals("tick_cmpr")) {
+ if (Name == "tick_cmpr") {
RegKind = SparcOperand::rk_Special;
return SP::ASR23;
}
- if (Name.equals("stick") || Name.equals("sys_tick")) {
+ if (Name == "stick" || Name == "sys_tick") {
RegKind = SparcOperand::rk_Special;
return SP::ASR24;
}
- if (Name.equals("stick_cmpr") || Name.equals("sys_tick_cmpr")) {
+ if (Name == "stick_cmpr" || Name == "sys_tick_cmpr") {
RegKind = SparcOperand::rk_Special;
return SP::ASR25;
}
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 2c2dc21f191d7a..62b4a9278954ce 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -2296,7 +2296,7 @@ bool X86AsmParser::ParseRoundingModeOp(SMLoc Start, OperandVector &Operands) {
Operands.push_back(X86Operand::CreateImm(RndModeOp, Start, End));
return false;
}
- if(Tok.getIdentifier().equals("sae")){
+ if (Tok.getIdentifier() == "sae") {
Parser.Lex(); // Eat the sae
if (!getLexer().is(AsmToken::RCurly))
return Error(Tok.getLoc(), "Expected } at this point");
@@ -2567,7 +2567,7 @@ bool X86AsmParser::ParseIntelMemoryOperandSize(unsigned &Size) {
.Default(0);
if (Size) {
const AsmToken &Tok = Lex(); // Eat operand size (e.g., byte, word).
- if (!(Tok.getString().equals("PTR") || Tok.getString().equals("ptr")))
+ if (!(Tok.getString() == "PTR" || Tok.getString() == "ptr"))
return Error(Tok.getLoc(), "Expected 'PTR' or 'ptr' token!");
Lex(); // Eat ptr.
}
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 3d80c43b571f9c..0e5e52d4d88e85 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -3570,7 +3570,7 @@ bool X86InstrInfo::canMakeTailCallConditional(
if (Target.isSymbol()) {
StringRef Symbol(Target.getSymbolName());
// this is currently only relevant to r11/kernel indirect thunk.
- if (Symbol.equals("__x86_indirect_thunk_r11"))
+ if (Symbol == "__x86_indirect_thunk_r11")
return false;
}
}
|
kuhar
approved these changes
May 5, 2024
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I'm planning to remove StringRef::equals in favor of
StringRef::operator==.
StringRef::operator==/!= outnumber StringRef::equals by a factor of
38 under llvm/ in terms of their usage.
The elimination of StringRef::equals brings StringRef closer to
std::string_view, which has operator== but not equals.
S == "foo" is more readable than S.equals("foo"), especially for
!Long.Expression.equals("str") vs Long.Expression != "str".