[TableGen][SubtargetEmitter] Refactor hasReadOfWrite to CodeGenProcModel #92032
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…l argument SubtargetEmitter::GenSchedClassTables takes a CodeGenProcModel, but calls hasReadOfWrite which loops over all ProcModels. We overload hasReadOfWrite to have a version that return true if the given write record is referenced by a ReadAdvance for the specified ProcModel. This leads to a 144% speedup on the RISC-V backend of our downstream. This patch is purley performance related has no impact on the final generated code.
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| if (!SchedModels.hasReadOfWrite( | ||
| SchedModels.getSchedWrite(WriteID).TheDef)) { | ||
| if (!SchedModels.hasReadOfWrite(SchedModels.getSchedWrite(WriteID).TheDef, | ||
| ProcModel)) { |
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The old code here checked all ProcModels not just this ProcModel. I'm surprised that this doesn't change the output.
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I am going to remove my statement that it does not change the output. It may change the output on some targets.
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After reviewing the code, I think if it did change the output everything would still work. For each Write for each ProcModel we are creating a vector of MCWriteLatencyEntry objects. Then we search a large vector to if that sequence of MCWriteLatencyEntry already exists in somewhere in SchedTables.WriteLatencies. If we find the sequence we save its index. If we don't find it, we append the vector we have to the end of SchedTables.WriteLatencies and save the index where it was appended. The index is used to find the sequence later at runtime.
In the usual case we probably find the sequence once we've created it for the first ProcModel. I think at worst, this patch would make us not find it for some ProcModel and cause it to be added at the end. I don't think would be a functional issue. It would just make SchedTables.WriteLatencies larger.
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✅ With the latest revision this PR passed the C/C++ code formatter. |
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…del (llvm#92032) SubtargetEmitter::GenSchedClassTables takes a CodeGenProcModel, but calls hasReadOfWrite which loops over all ProcModels. We move hasReadOfWrite to CodeGenProcModel and remove the loop over all ProcModels. This leads to a 144% speedup on the RISC-V backend of our downstream.
SubtargetEmitter::GenSchedClassTables takes a CodeGenProcModel, but calls hasReadOfWrite which loops over all ProcModels. We move hasReadOfWrite to CodeGenProcModel and remove the loop over all ProcModels. This leads to a 144% speedup on the RISC-V backend of our downstream.