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Postcommit fixes for histogram intrinsic #92095

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May 14, 2024
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4 changes: 2 additions & 2 deletions llvm/docs/LangRef.rst
Original file line number Diff line number Diff line change
Expand Up @@ -19143,8 +19143,8 @@ will be on any later loop iteration.
This intrinsic will only return 0 if the input count is also 0. A non-zero input
count will produce a non-zero result.

'``llvm.experimental.vector.histogram.*``' Intrinsics
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
'``llvm.experimental.vector.histogram.*``' Intrinsic
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

These intrinsics are overloaded.

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14 changes: 8 additions & 6 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -27395,9 +27395,11 @@ SDValue AArch64TargetLowering::LowerVECTOR_HISTOGRAM(SDValue Op,
SDValue IncSplat = DAG.getSplatVector(MemVT, DL, Inc);
SDValue Ops[] = {Chain, PassThru, Mask, Ptr, Index, Scale};

// Set the MMO to load only, rather than load|store.
MachineMemOperand *GMMO = HG->getMemOperand();
GMMO->setFlags(MachineMemOperand::MOLoad);
MachineMemOperand *MMO = HG->getMemOperand();
// Create an MMO for the gather, without load|store flags.
MachineMemOperand *GMMO = DAG.getMachineFunction().getMachineMemOperand(
MMO->getPointerInfo(), MachineMemOperand::MOLoad, MMO->getSize(),
MMO->getAlign(), MMO->getAAInfo());
ISD::MemIndexType IndexType = HG->getIndexType();
SDValue Gather =
DAG.getMaskedGather(DAG.getVTList(MemVT, MVT::Other), MemVT, DL, Ops,
Expand All @@ -27412,10 +27414,10 @@ SDValue AArch64TargetLowering::LowerVECTOR_HISTOGRAM(SDValue Op,
SDValue Mul = DAG.getNode(ISD::MUL, DL, MemVT, HistCnt, IncSplat);
SDValue Add = DAG.getNode(ISD::ADD, DL, MemVT, Gather, Mul);

// Create a new MMO for the scatter.
// Create an MMO for the scatter, without load|store flags.
MachineMemOperand *SMMO = DAG.getMachineFunction().getMachineMemOperand(
GMMO->getPointerInfo(), MachineMemOperand::MOStore, GMMO->getSize(),
GMMO->getAlign(), GMMO->getAAInfo());
MMO->getPointerInfo(), MachineMemOperand::MOStore, MMO->getSize(),
MMO->getAlign(), MMO->getAAInfo());

SDValue ScatterOps[] = {GChain, Add, Mask, Ptr, Index, Scale};
SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), MemVT, DL,
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2 changes: 1 addition & 1 deletion llvm/lib/Transforms/Scalar/ScalarizeMaskedMemIntrin.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1006,7 +1006,7 @@ static bool optimizeCallInst(CallInst *CI, bool &ModifiedDT,
CI->getArgOperand(1)->getType()))
return false;
scalarizeMaskedVectorHistogram(DL, CI, DTU, ModifiedDT);
break;
return true;
case Intrinsic::masked_load:
// Scalarize unsupported vector masked load
if (TTI.isLegalMaskedLoad(
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