Update benchmarks.

lnis-uofu · Mar 21, 2022 · deb3cdd · deb3cdd
1 parent d9fbb47
commit deb3cdd
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Showing 50 changed files with 175,414 additions and 733 deletions.
diff --git a/benchmarks/.gitignore b/benchmarks/.gitignore
@@ -1,8 +1,20 @@
-*_lsoracle.*
-*_aigscript.*
-*_migscript.*
-*_abc.*
-*_unoptimized.*
+*.lsoracle.*
+*.aigscript.*
+*.migscript.*
+*.abc.*
+
+*.direct_ndp.*
+*.mixed.*
+*.unoptimized.*
+*.xmgscript.*
+*.redux.*
+*.timing2.*
+*.timing.*
+*.timing_direct*.*
+*.timing_yosys*.*
+*.redux_*.*
+*.xmg2.*
+*.xmg3.*
 *.mapped.v
 *.aig
 *.report
@@ -12,3 +24,16 @@
 *.pdf
 *.log
 *.rtl
+*_timing.*
+*.lsoracle.script
+*.yosys.script
+*.abc.script
+*.blif
+*.parts
+*.synth.v
+*.json
+*.gates
+*.script
+formality_workdir
+techmapping/gf12/*.lib
+techmapping/gf12/*.db
diff --git a/benchmarks/Makefile b/benchmarks/Makefile
diff --git a/benchmarks/ibex/ibex.sdc b/benchmarks/ibex/ibex.sdc
@@ -1,34 +1,3 @@
-create_clock -name clk -period 10 {clk_i}
-set_input_delay -clock clk 0 {
-test_en_i
-rst_ni
-irq_timer_i
-irq_software_i
-irq_nm_i
-irq_fast_i
-irq_external_i
-instr_rvalid_i
-instr_rdata_i
-instr_gnt_i
-instr_err_i
-hart_id_i
-fetch_enable_i
-debug_req_i
-data_rvalid_i
-data_rdata_i
-data_gnt_i
-data_err_i
-boot_addr_i
-}
-set_output_delay -clock clk 0 {
-instr_req_o
-instr_addr_o
-data_we_o
-data_wdata_o
-data_req_o
-data_be_o
-data_addr_o
-core_sleep_o
-alert_minor_o
-alert_major_o
-}
+create_clock -name clk -period 10 {clk}
+set_input_delay -clock clk -max 0 [all_inputs]
+set_output_delay -clock clk -max 0 [all_outputs]
diff --git a/benchmarks/ibex/ibex.v b/benchmarks/ibex/ibex.v
@@ -1475,7 +1475,7 @@ module ibex_controller (
 	end
 endmodule
 module ibex_core (
-	clk_i,
+	clk,
 	rst_ni,
 	test_en_i,
 	hart_id_i,
@@ -1528,7 +1528,7 @@ module ibex_core (
 	parameter [0:0] SecureIbex = 1'b0;
 	parameter [31:0] DmHaltAddr = 32'h1a110800;
 	parameter [31:0] DmExceptionAddr = 32'h1a110808;
-	input wire clk_i;
+	input wire clk;
 	input wire rst_ni;
 	input wire test_en_i;
 	input wire [31:0] hart_id_i;
@@ -1715,27 +1715,27 @@ module ibex_core (
 	wire perf_store;
 	wire illegal_insn_id;
 	wire unused_illegal_insn_id;
-	wire clk;
+	wire clk_o;
 	wire clock_en;
 	assign core_busy_d = (ctrl_busy | if_busy) | lsu_busy;
-	always @(posedge clk_i or negedge rst_ni)
+	always @(posedge clk or negedge rst_ni)
 		if (!rst_ni)
 			core_busy_q <= 1'b0;
 		else
 			core_busy_q <= core_busy_d;
 	reg fetch_enable_q;
-	always @(posedge clk_i or negedge rst_ni)
+	always @(posedge clk or negedge rst_ni)
 		if (!rst_ni)
 			fetch_enable_q <= 1'b0;
 		else if (fetch_enable_i)
 			fetch_enable_q <= 1'b1;
 	assign clock_en = fetch_enable_q & (((core_busy_q | debug_req_i) | irq_pending) | irq_nm_i);
 	assign core_sleep_o = ~clock_en;
 	prim_clock_gating core_clock_gate_i(
-		.clk_i(clk_i),
+		.clk_i(clk),
 		.en_i(clock_en),
 		.test_en_i(test_en_i),
-		.clk_o(clk)
+		.clk_o(clk_o)
 	);
 	localparam [31:0] ibex_pkg_PMP_I = 0;
 	ibex_if_stage #(
@@ -1747,7 +1747,7 @@ module ibex_core (
 		.PCIncrCheck(PCIncrCheck),
 		.BranchPredictor(BranchPredictor)
 	) if_stage_i(
-		.clk_i(clk),
+		.clk_i(clk_o),
 		.rst_ni(rst_ni),
 		.boot_addr_i(boot_addr_i),
 		.req_i(instr_req_int),
@@ -1805,7 +1805,7 @@ module ibex_core (
 		.WritebackStage(WritebackStage),
 		.BranchPredictor(BranchPredictor)
 	) id_stage_i(
-		.clk_i(clk),
+		.clk_i(clk_o),
 		.rst_ni(rst_ni),
 		.ctrl_busy_o(ctrl_busy),
 		.illegal_insn_o(illegal_insn_id),
@@ -1923,7 +1923,7 @@ module ibex_core (
 		.RV32B(RV32B),
 		.BranchTargetALU(BranchTargetALU)
 	) ex_block_i(
-		.clk_i(clk),
+		.clk_i(clk_o),
 		.rst_ni(rst_ni),
 		.alu_operator_i(alu_operator_ex),
 		.alu_operand_a_i(alu_operand_a_ex),
@@ -1954,7 +1954,7 @@ module ibex_core (
 	assign data_req_o = data_req_out & ~pmp_req_err[ibex_pkg_PMP_D];
 	assign lsu_resp_err = lsu_load_err | lsu_store_err;
 	ibex_load_store_unit load_store_unit_i(
-		.clk_i(clk),
+		.clk_i(clk_o),
 		.rst_ni(rst_ni),
 		.data_req_o(data_req_out),
 		.data_gnt_i(data_gnt_i),
@@ -1985,7 +1985,7 @@ module ibex_core (
 		.perf_store_o(perf_store)
 	);
 	ibex_wb_stage #(.WritebackStage(WritebackStage)) wb_stage_i(
-		.clk_i(clk),
+		.clk_i(clk_o),
 		.rst_ni(rst_ni),
 		.en_wb_i(en_wb),
 		.instr_type_wb_i(instr_type_wb),
@@ -2068,7 +2068,7 @@ module ibex_core (
 				.DataWidth(RegFileDataWidth),
 				.DummyInstructions(DummyInstructions)
 			) register_file_i(
-				.clk_i(clk_i),
+				.clk_i(clk),
 				.rst_ni(rst_ni),
 				.test_en_i(test_en_i),
 				.dummy_instr_id_i(dummy_instr_id),
@@ -2087,7 +2087,7 @@ module ibex_core (
 				.DataWidth(RegFileDataWidth),
 				.DummyInstructions(DummyInstructions)
 			) register_file_i(
-				.clk_i(clk_i),
+				.clk_i(clk),
 				.rst_ni(rst_ni),
 				.test_en_i(test_en_i),
 				.dummy_instr_id_i(dummy_instr_id),
@@ -2106,7 +2106,7 @@ module ibex_core (
 				.DataWidth(RegFileDataWidth),
 				.DummyInstructions(DummyInstructions)
 			) register_file_i(
-				.clk_i(clk_i),
+				.clk_i(clk),
 				.rst_ni(rst_ni),
 				.test_en_i(test_en_i),
 				.dummy_instr_id_i(dummy_instr_id),
@@ -2143,7 +2143,7 @@ module ibex_core (
 		.RV32E(RV32E),
 		.RV32M(RV32M)
 	) cs_registers_i(
-		.clk_i(clk),
+		.clk_i(clk_o),
 		.rst_ni(rst_ni),
 		.hart_id_i(hart_id_i),
 		.priv_mode_id_o(priv_mode_id),
@@ -2228,7 +2228,7 @@ module ibex_core (
 				.PMPNumChan(PMP_NUM_CHAN),
 				.PMPNumRegions(PMPNumRegions)
 			) pmp_i(
-				.clk_i(clk),
+				.clk_i(clk_o),
 				.rst_ni(rst_ni),
 				.csr_pmp_cfg_i(csr_pmp_cfg),
 				.csr_pmp_addr_i(csr_pmp_addr),

diff --git a/benchmarks/iscas89/s298.sdc b/benchmarks/iscas89/s298.sdc
@@ -1,5 +1,14 @@
-create_clock -name clk -period 10 {clk_i}
+create_clock -name clk -period 10 {CK}
 set_input_delay -clock clk 0 {
+G2
+G1
+G0
 }
 set_output_delay -clock clk 0 {
+G67
+G66
+G133
+G132
+G118
+G117
 }
diff --git a/benchmarks/picorv32/picorv32.sdc b/benchmarks/picorv32/picorv32.sdc
@@ -1,28 +1,3 @@
-create_clock -name clk -period 10 {wb_clk_i}
-set_input_delay -clock clk 0 {
-wbm_dat_i
-wbm_ack_i
-wb_rst_i
-pcpi_wr
-pcpi_wait
-pcpi_ready
-pcpi_rd
-irq
-}
-set_output_delay -clock clk 0 {
-wbm_we_o
-wbm_stb_o
-wbm_sel_o
-wbm_dat_o
-wbm_cyc_o
-wbm_adr_o
-trap
-trace_valid
-trace_data
-pcpi_valid
-pcpi_rs2
-pcpi_rs1
-pcpi_insn
-mem_instr
-eoi
-}
+create_clock -name clk -period 1 {clk}
+set_input_delay -clock clk -max 0 [all_inputs]
+set_output_delay -clock clk -max 0 [all_outputs]
diff --git a/benchmarks/picorv32/picorv32.v b/benchmarks/picorv32/picorv32.v
@@ -2838,7 +2838,7 @@ module picorv32_wb #(
 
 	// Wishbone interfaces
 	input wb_rst_i,
-	input wb_clk_i,
+	input clk,
 
 	output reg [31:0] wbm_adr_o,
 	output reg [31:0] wbm_dat_o,
@@ -2901,7 +2901,6 @@ module picorv32_wb #(
 	wire clk;
 	wire resetn;
 
-	assign clk = wb_clk_i;
 	assign resetn = ~wb_rst_i;
 
 	picorv32 #(
@@ -2990,7 +2989,7 @@ module picorv32_wb #(
 	wire we;
 	assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]);
 
-	always @(posedge wb_clk_i) begin
+	always @(posedge clk) begin
 		if (wb_rst_i) begin
 			wbm_adr_o <= 0;
 			wbm_dat_o <= 0;