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Adding vpr tcl #681

Merged
merged 7 commits into from
Jun 10, 2022
Merged

Adding vpr tcl #681

merged 7 commits into from
Jun 10, 2022

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ManadherRS
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Motivate of the pull request

  • Adding a tcl interface starter to vpr to allow tcl scripting
  • The library libvpr.so should be loaaded using LD_LIBRARY_PATH .

Describe the technical details

-[ ]

What is currently done? (Provide issue link if applicable)

  • The available tcl commands call the pack, place, route,and analyse flows
  • more limitations

What does this pull request change?

Which part of the code base require a change

  • [ x] VPR
  • Tileable routing architecture generator
  • OpenFPGA libraries
  • FPGA-Verilog
  • FPGA-Bitstream
  • FPGA-SDC
  • FPGA-SPICE
  • Flow scripts
  • Architecture library
  • Cell library
  • Documentation
  • Regression tests
  • Continous Integration (CI) scripts

Impact of the pull request

  • Require a change on Quality of Results (QoR)
  • Break back-compatibility. Use LD_LIBRARY_PATH to point to libvpr.so

@tangxifan
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@ganeshgore Can you help @ManadherRS on the errors in integration?
He is bringing tcl interface for VTR here and we will extend it to the OpenFPGA tools.
He is facing some issues on installing dependencies and lib.so to docker image.

  • He needs to install SWIG as a dependency for compilation
  • He also needs to have the libvpr.so in the docker image when running regression tests.

Let me know if you have any question.

@ganeshgore
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@tangxifan Sure.

@ManadherRS Can we split this PR into two parts?. The first part just consists of libs/EXTERNAL/TCLxxx
and second with all remaining changes. It will simplify the review process.

@ganeshgore ganeshgore merged commit c37ce51 into master Jun 10, 2022
@tangxifan tangxifan deleted the adding_vpr_tcl branch June 10, 2022 01:35
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3 participants