[pcie_core] Cannot access DDR data from high address

[lerwys]

Problem: We can't read data from DDR from pages larger than 10-bits.

The problem appears when I try to read the DDR memory from AFCv3 through
PCIe. As I'm aware the DDR size is 4 GB (2^30 words of 32 bit = 4GB), right?

With that in mind I'm trying to read from DDR page 896, for instance. This gives us
1110000000 in binary, which are 10 bits. So far, so good.

When I try to read from DDR page 1152, which is 10010000000 (11 bits) in binary,
I don't get any valid data, just garbage.

Having a look at rx_MRd_Channel.vhd, which is located in https://github.com/lnls-dig/bpm-gw/blob/devel/hdl/modules/pcie/common/rx_MRd_Channel.vhd (I don't know if this is the
right place to look for this issue) file I see the following lines where sdram_pg is used:

392 pioCplD_din(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT)                  
393   <= sdram_pg(C_CHBUF_DDA_BIT_TOP-C_CHBUF_DDA_BIT_BOT-C_DDR_PG_WIDTH downto 0) &
394       m_axis_rx_tdata_r1(C_DDR_PG_WIDTH-1+32 downto 0+32);
...
412 pioCplD_din(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT)       
413   <= sdram_pg(C_CHBUF_DDA_BIT_TOP-C_CHBUF_DDA_BIT_BOT-C_DDR_PG_WIDTH downto 0) &  
414       m_axis_rx_tdata_r1(C_DDR_PG_WIDTH-1 downto 0); 

If my math is correct sdram_pg(C_CHBUF_DDA_BIT_TOP-C_CHBUF_DDA_BIT_BOT-C_DDR_PG_WIDTH downto 0) translates to sdram_pg(9 downto 0), which has only the 10 LSB.

[augustofg]

Is this still an issue? @ericonr

[ericonr]

As I'm aware the DDR size is 4 GB (2^30 words of 32 bit = 4GB), right?

I believe this is incorrect, because the DDR size is 2GB. Either way, being limited to 10 bits would still restrict us to 1GB of it.

Does it make sense to test this with the AFCv4, or should it be with the BPM gateware specifically?