Fix constraints update IP cores #33
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- clk_fast_spi is a TCl variable, so when using set_clock_groups it should be expanded with a '$'; - clk_fast_spi and clk_adcdac_ref are asynchronous between each other, remove the 'set_max_delay' commands between them; - clk_fast_spi and rtmlamp_adc_octo_sck or rtmlamp_adc_quad_sck are asynchronous between each other, remove the 'set_max_delay' commands between them;
Makes timing closure easier.
This should lead to a more efficient DSP inference, possibly fixing some time closures problems. Also register the inputs of dot_prod.
Update CommsCtrlFPGA and infra-cores submodules to include the updated xci IP cores for Vivado 2022.2, add the ExtraTimingOpt flag to make timing closure possible.
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