Name		Name	Last commit message	Last commit date
Latest commit History 134 Commits
4-bit		4-bit
8-bit FPGA		8-bit FPGA
8-bit Synchoronous Counter		8-bit Synchoronous Counter
07_mux_2_1.v		07_mux_2_1.v
4-bit-FA.v		4-bit-FA.v
4-bit-FA_bh.v		4-bit-FA_bh.v
4-bit-FA_df.v		4-bit-FA_df.v
4-bit_comparator_bh.v		4-bit_comparator_bh.v
4-bit_comparator_df1.v		4-bit_comparator_df1.v
4-bit_comparator_df2.v		4-bit_comparator_df2.v
5-bit_shift_reg.v		5-bit_shift_reg.v
FullAdderST1.v		FullAdderST1.v
FullAdderST2.v		FullAdderST2.v
FullAdderST3.v		FullAdderST3.v
FullAdder_st.v		FullAdder_st.v
FullAdder_st2.v		FullAdder_st2.v
FullAdder_st3.v		FullAdder_st3.v
Full_Adder_Dataflow.v		Full_Adder_Dataflow.v
Full_Adder_bh.v		Full_Adder_bh.v
Full_Adder_bh_tb.v		Full_Adder_bh_tb.v
README.md		README.md
alu32behaviour.v		alu32behaviour.v
barrel_bh.v		barrel_bh.v
counter_10to40_up.v		counter_10to40_up.v
counter_10to40_up_down.v		counter_10to40_up_down.v
counter_up_basic_tb.v		counter_up_basic_tb.v
counter_up_load.v		counter_up_load.v
d-latch_df.v		d-latch_df.v
d_flip-flop.v		d_flip-flop.v
d_flipflop.v		d_flipflop.v
d_latch.v		d_latch.v
decode_3_8_df.v		decode_3_8_df.v
decoder_2_4.v		decoder_2_4.v
design.mod.v		design.mod.v
dff.v		dff.v
dff_slr_shs.v		dff_slr_shs.v
dffb1.v		dffb1.v
dffbb.v		dffbb.v
dffbbb.v		dffbbb.v
dffbed.v		dffbed.v
digital_design.v		digital_design.v
dlatch_bh.v		dlatch_bh.v
dlatch_bha.v		dlatch_bha.v
dram.v		dram.v
encode_4-2_bh.v		encode_4-2_bh.v
encode_4_2_DF.v		encode_4_2_DF.v
encode_4_2_pBH.v		encode_4_2_pBH.v
encode_4_2_pdf.v		encode_4_2_pdf.v
ex.v		ex.v
freq_divider.v		freq_divider.v
fsm_1101.v		fsm_1101.v
full_Adder.v		full_Adder.v
half_adder.v		half_adder.v
half_adder_DataFlow.v		half_adder_DataFlow.v
halfadder.v		halfadder.v
halfadder_bh.v		halfadder_bh.v
halfadder_st.v		halfadder_st.v
helloWorld.v		helloWorld.v
high_dffb.v		high_dffb.v
input [net_type] [range] list_of_name;.v		input [net_type] [range] list_of_name;.v
jk_ff.v		jk_ff.v
license		license
low_dffb.v		low_dffb.v
low_dffbasy.v		low_dffbasy.v
mealy_seq_001.v		mealy_seq_001.v
minor_8-bit-synchoronous-counter.v		minor_8-bit-synchoronous-counter.v
mod_counter.v		mod_counter.v
module (input a,.v		module (input a,.v
module des ( input clk,.v		module des ( input clk,.v
module des ( input clk.v		module des ( input clk.v
module des ().v		module des ().v
module full_adder_4bit_bh_tb.v		module full_adder_4bit_bh_tb.v
module mod3 ([port_list]);.v		module mod3 ([port_list]);.v
module my_design (input wire clk,.v		module my_design (input wire clk,.v
module shift_reg ( input d.v		module shift_reg ( input d.v
module test (a, b, c);.v		module test (a, b, c);.v
module testbench;.v		module testbench;.v
module-testbench.v		module-testbench.v
module.v		module.v
module_mux_2_1.v		module_mux_2_1.v
module_mux_2_1_tb.v		module_mux_2_1_tb.v
module_testbench.v		module_testbench.v
moduledes.v		moduledes.v
moore_seq_001.v		moore_seq_001.v
mux.v		mux.v
mux_2_1_df.v		mux_2_1_df.v
mux_2_1_df_bh.v		mux_2_1_df_bh.v
mux_2_1bh.v		mux_2_1bh.v
mux_2x1_bh.v		mux_2x1_bh.v
mux_3_ways.v		mux_3_ways.v
mux_4_1_df.v		mux_4_1_df.v
mux_4_1_dff.v		mux_4_1_dff.v
mux_4_1_dfff.v		mux_4_1_dfff.v
parameterised_counter.v		parameterised_counter.v
posedge.v		posedge.v
ram_dual_port.v		ram_dual_port.v
ram_single_port.v		ram_single_port.v
reg_set.v		reg_set.v
set_reset_ff.v		set_reset_ff.v
single_port_ram.v		single_port_ram.v

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Verilog

This is my verilog practice which i do while i learning verilog...

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look4raghav/Verilog

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