Ugly workarounds for Loongson-3

1, Remove redundant sync in llsc; 2, Use synci as smp_llsc_mb() for new Loongson-3.
loongson-community · Aug 17, 2018 · 8364491 · 8364491
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commit 8364491
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diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h
@@ -209,7 +209,11 @@
 #define __WAR_LLSC_MB		"		\n"
 #endif
 
+#ifndef CONFIG_LOONGSON3_ENHANCEMENT
 #define smp_llsc_mb()	__asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
+#else
+#define smp_llsc_mb()	__asm__ __volatile__(".set mips64r2\n synci 0\n .set mips0\n" : : :"memory")
+#endif
 
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 #define smp_mb__before_llsc() smp_wmb()

diff --git a/arch/mips/loongson64/Platform b/arch/mips/loongson64/Platform
@@ -26,6 +26,9 @@ cflags-$(CONFIG_CPU_LOONGSON3)	+= -Wa,--trap
 ifneq ($(call as-option,-Wa$(comma)-mfix-loongson3-llsc,),)
   cflags-$(CONFIG_CPU_LOONGSON3) += -Wa$(comma)-mno-fix-loongson3-llsc
 endif
+ifneq ($(call as-option,-Wa$(comma)-mfix-ls3a-llsc,),)
+  cflags-$(CONFIG_CPU_LOONGSON3) += -Wa$(comma)-mnofix-ls3a-llsc
+endif
 #
 # binutils from v2.25 on and gcc starting from v4.9.0 treat -march=loongson3a
 # as MIPS64 R2; older versions as just R1.  This leaves the possibility open