[top_earlgrey] Timing optimizations for production

[andreaskurth]

This is a tracker for timing optimizations for Earlgrey-PROD.

Planned for M3:

• Decouple sram_ctrl's a_ready TL-UL signal from a_valid
  --> [sram_ctrl/rtl] Timing fixes #22497
• Decouple sram_ctrl's a_ready TL-UL signal from a_opcode (through tlul_we)
  --> [sram_ctrl/rtl] Timing fixes #22497
• Break path from tl_i to tl_o in tlul_sram_adapter
  --> [tlul/rtl] Fix SRAM timing #22588
• Rework tlul_err_resp
  --> [tlul/rtl] Fix SRAM timing #22588
• Reduce the number of PRINCE rounds for the ICache scrambling back to 5 effective rounds.
  --> [rv_core_ibex] Re-vendor Ibex and reduce number of PRINCE rounds for ICache scrambling #22948

[vogelpi]

Update: PRs to fix all feedthrough paths between Ibex and SRAM_CTRL (the critical path of the design) were filed and merged, an RC was tagged and sent to the PD team to trigger a new synthesis run and the generation of a timing report. We're now waiting for feedback.

[andreaskurth]

By @vogelpi: Discussed with PD team yesterday, feedback pending.

By @andreaskurth: Timing closure for M3 is not required. Can be moved to M4 if needed.

By @moidx: That would be my recommendation as well, given the timeline.

[vogelpi]

Update: we got feedback from the PD team. There are some violations left between the ICache and the main SRAM that we can hopefully get rid of by reducing the number of scrambling rounds in the ICache again. This is acceptable from a security viewpoint.