[spi_host, dv] V2S signoff

[antmarzam]

Description

Get spi_host ready for V2S signoff and sign it off

[antmarzam]

DESIGN_DELTAS_CAPTURED_V2

List of commits since ES. The list has been compiled via:

git log Earlgrey-M2.5.2-RC0..HEAD hw/ip/spi_host/ hw/dv/sv/spi_agent/

Newer commits at the top (reverts have been removed):

• d268f27 [spi_host/doc]: Correct RST -> SW_RST typo
  • doc change
• ee5f4a1 [sram_ctrl] Add readback feature
  • RTL sram_ctrl change
• 11107d5 [spi_host] Disable FWFT for the command queue
  • RTL change - Eliminates First Word Fallthrough in command queue
• 12f6088 [dv] spi_device_scoreboard flash_status fix
  • spi_agent comment cleanup
• 432200b [dv] spi_monitor fix:
  • spi_agent fix (related to spi_device upbringing)
• dc848b3 [sram_ctrl,prim,rtl] Fix tlul_we -> ready timing path.
  • sram_ctrl, prim RTL changes
• 66f99a7 [spi_host,doc] Cleanup readme and theory-of-operations
  • doc cleanup
• ed56f75 [spi_host,doc] Move misplaced doc sections around, fixup errors
  • Doc fixup
• 45b6e02 [spi_host,doc] Update diagrams to seperate passthrough mux
  • Doc diagram update
• 8295903 [bazel,autogen_hjson] Split C and rust header generation
  • Bazel change
• 30d7e78 Add the project name to the copyright header
• f4c2bb9 Remove trailing whitespaces
• a5ce859 [spi_host,doc] Clarify that the 'spi_event' interrupt is Status-Type
  • doc change
• 3e9cb7b [spi_host,dv] Update testplan based on D2(S) changes
  • testplan change
• ec43583 [dv] intercept sequence && intr_status stimulus update
  • DV changes to spi_agent (related to spi_device upbringing)
• 42dfffe [dv] flash_status dynamically updated TB update
  • DV changes to spi_agent (related to spi_device upbringing)
• 9868fa8 [spi_host] Downgrade verification_stage to V1
  • Sing-off criteria was downgraded to V1
• 508cd2f [spi_host] Correct TXFULL description
  • DOC typo fix
• 18b0ced [dv] Remove phase argument from monitor's collect_trans
  • common DV fix across the project
• 6e12735 [spi_host] Fix "bute"/"byte" typo in registers
  • doc change
• e3ca274 [spi_host,rtl] Use sd_en_o[0] to only drive sd_o[0] during TX (std_mode)
  • RTL change
• f7fc348 [spi_host,rtl] Change 'spi_event' interrupt to CIP 'Status' type
  • RTL+SW+Doc change
• 369be91 [spi_host,doc] Regenerate register documentation
  • doc change
• 272787c [spi_host,rtl] Factor the byte_sel block into TX FIFO status signals
  • RTL+DV+doc to incorporate byte select signal into TX FIFO status
• 0d14dd6 [docs] Fix repetitions of the definite article
  • doc change
• 61a237e [util/reggen] reverse order of substruct generation
  • reggen order reversed
• fc84846 [reggen,hw] Create index parameter for registers windows
  • Add Index parameters to RTL reg package
• de31bdf [reggen] Remove the devmode input
  • devmode input remove from exclusions top-level, reg_top and README
• 963a500 [doc] Minor tweak to md sanitisation code
  • doc cleanup
• 975a6eb [adc_ctrl,dv] Tidy up access to intr_state in env_cfg files
  • Code tidy up
• 3f128e7 [spi_host] Add feature list for block
  • Feature list added to spi_host.hjson
• 1b16ca2 [reggen] Add mubi support SWAccess that sets/clears a reg
  • RTL reg change
• 59f8142 [doc] Moved badges over to using hosted images
  • doc change
• 8c77234 [doc] spi_host registers and interfaces now use CMDGEN
  • doc change
• 7688e71 [reggen] Add initial support for version and cip_id hjson fields
  • Regtool change

Apart from the above, the following spi_host PRs are open as of now:

• RTL PRs:
  • [spi_host, rtl] Spi host sd_en_o stable through the entire cycle (fsm fix) #23476
• SW PRs:
  • Add ROM/ROM_EXT drivers for SPI_HOST and SPI NOR Flash #20358
• DV PRs:
  • [spi_host, dv] Spi host data_line stable check + allowing non-golden stimulus to occur #23174
  • [spi_host,dv] Fix some typing problems in spi_host DV code #22144

DV_DOC_COMPLETED
All RTL changes have been reflected in the spec

FUNCTIONAL_COVERAGE_IMPLEMENTED
Yes

ALL_INTERFACES_EXERCISED
Yes

ALL_ASSERTION_CHECKS_ADDED
There's an SVA based check in PR

SIM_TB_ENV_COMPLETED
Yes

SIM_ALL_TESTS_PASSING
Not true in an absolute manner but true for our metrics. Latest regression run had a passing rate of 684/690

SIM_NIGHTLY_REGRESSION_V2
Yes

SIM_CODE_COVERAGE_V2
CCOV is over 90%, branch coverage is the lowest at 92%

SIM_FUNCTIONAL_COVERAGE_V2
Yes, current metric is 90.87% for FCOV

SEC_CM_PLANNED
Yes, and already implemented

NO_HIGH_PRIORITY_ISSUES_PENDING, ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED
P1 issue : But there are currently 2 PR opened (mentioned above) one for DV one for RTL

DV_DOC_TESTPLAN_REVIEWED
Yes

V3_CHECKLIST_SCOPED
The checklist hasn't been scoped, but given the coverage numbers (shown below). I anticipate an effort of up to 2-3 weeks to close coverage and do the necessary cleanup

Coverage numbers as of 4/6/24:

Note: FPV and SIM_FW_SIMULATED have been removed from above list since they don't apply to spi device.

[antmarzam]

V3 checklist scoping:

X_PROP_ANALYSIS_COMPLETED:

There are RTL blocks reported as disabled for XPROP, but these are not RTL blocks, just refer to code which isn't synthesizable.

SIM_NIGHTLY_REGRESSION_AT_V3:

We have no testing enabled at V3 level, presumably due to the failing rate of spi_host_stress_all_with_rand_reset - @hcallahan-lowrisc Do you have a view on how long getting these test to 100%?
The rest of the regression is in decent shape, with the lowest passing rate at 88% for spi_host_status_stall

SIM_CODE_COVERAGE_AT_100:

1 week of estimate effort

SIM_FUNCTIONAL_COVERAGE_AT_100:

1 week of estimate effort

ALL_TODOS_RESOLVED:

P2 issue currently wraps all TODOs: #18886
This also includes enabling V3 tests, which is estimated above.
I would say 1-2 days for this - @hcallahan-lowrisc: do you agree?

NO_TOOL_WARNINGS_THROWN:

0.5 day

TB_LINT_COMPLETE:

Already satisfied

[antmarzam]

cc @rswarbrick @hcallahan-lowrisc

[johngt]

Thanks for the summary @antmarzam - it looks like #23476 is the main thing to get in as a priority.

[antmarzam]

Thank you guys!
Before we can sign-off the module, we have the following action items from V2/V2S meeting:

• RTL PR needs to be in master
• DV changes need to be in master
• data_fifo_status testpoint is not linked to any tests. (Can be mapped to existing tests)

HC(edit): Based on discussion in the review, we believe this RTL change + associated DV fix are low risk for an RTL freeze, but to the letter of the review criteria they should be completed for signoff.

[rswarbrick]

Following up on this:

• The two tracked DV changes are merged ([spi_host,dv] Fix some typing problems in spi_host DV code #22144, [spi_host, dv] Spi host data_line stable check + allowing non-golden stimulus to occur #23174)
• The data_fifo_status testpoint is now mapped to the spi_host_overflow_underflow test (the mapping came with 274fcc7)

I'm satisfied that the verification stage can be bumped back up to V2S. @antmarzam, would you mind filing a PR to do so? (This just needs to change spi_host.hjson)