Git repository for the Introduction to FPGA Programming Using Xilinx Vivado and VHDL (4 CFU) PhD course at University of Torino, Physics Department.
- Contacts
- Course program
- Course material
- Hands-on laboratories
- Environment setup
- Git installation and configuration
- Clone and update the Git repository for the course
- Basic git commands
- Sample Xilinx Vivado simulation and implementation flows
- Reference documentation
- Webex lectures
University of Torino, Physics Department
via Pietro Giuria 1, 10125, Torino, Italy
Email: pacher@NOSPAMto.infn.it
Office: new building, 3rd floor, room C4
Phone: +39.011.670.7477
Webex: https://unito.webex.com/meet/luca.pacher
This is a postgraduate introductory course about digital design and FPGA programming using Xilinx Vivado
and the VHDL Hardware Description Language (HDL).
The main topics covered in the course are:
- VHDL syntax fundamentals, HDL design flow
- logic values, resolved vs. unresolved logic values, 3-state logic, buses and endianess
- review of boolean algebra
- introduction to Xilinx Vivado simulation and implementation flows
- design and simulation of combinational circuits with VHDL examples (multiplexers, decoders, encoders etc.)
- FPGA architectures overview and basic building blocks (fabric, BEL, LUT, CLB, CLA, slices, IOBs, hard-macros)
- introduction to Xilinx Design Constraints (XDCs)
- sequential circuits, latches and FlipFlops
- counters, registers, Pulse-Width Modulation (PWM), shift-registers, FSM, FIFOs, RAM/ROM
- advanced Xilinx Design Constraints (XDCs) and timing fundamentals
- synchronous design good and bad practices, example Vivado IP flows (clock wizard, FIFO compiler)
- gate-level simulations with back-annotated delays (SDF)
- practical implementation and test of small digital systems targeting a Xilinx Artix-7 FPGA device
IMPORTANT !
All students are requested to complete the preparatory work before attending practical lectures !
Please go through detailed step-by-step instructions presented in labs/lab0/README.md
Lecture slides are available at:
http://personalpages.to.infn.it/~pacher/teaching/FPGA/phd/slides
A complete list of reference documentation and online resources is available in the Reference documentation
section instead.
Board schematics can be found in the main doc/ directory of the repository.
Additional software components for Windows can be downloaded from:
http://personalpages.to.infn.it/~pacher/teaching/FPGA/software/windows
Links to recorded video lectures are listed in the Webex lectures section.
The course is organized in form of virtual laboratories to introduce fundamental concepts in FPGA design
and simulation using the VHDL Hardware Description Language (HDL) and Xilinx Vivado.
Each "lab" consists of step-by-step instructions to guide the student in running the simulation and implementation flows using Xilinx tools from the command-line.
The only requirement for these labs is to have a personal computer with all necessary development tools properly installed and configured.
The complete list of proposed labs can be found here.
Virtual laboratories are then supported by practical examples in the electronics lab in order to let students to physically experiment with a real FPGA and digital circuits using real hardware and instrumentation.
IMPORTANT !
Each student is requested to have a fully-working FPGA development environment installed on his/her
personal computer in terms of software installations, licensing, command-line setup etc.
Please complete the preparatory work by going through detailed step-by-step instructions presented
in fpga/labs/lab0/README.md well before attending the first lecture!Be aware that Xilinx only supports Linux and Windows platforms, not MacOS. Students using a MacOS personal computer must either install a supported operating system (Linux Ubuntu would be preferable) using a dual-boot or a virtualization software (VirtualBox is fine) or find another computer running a Linux distribution or Windows 7/10.
In this introductory course we will adopt a script-based and command-line based approach to FPGA programming using Xilinx Vivado assuming a Linux-like development environment.
Both Linux and Windows operating systems are supported.
Familiarity with Linux basic shell commands to work with files and directories (pwd, cd, ls, cp, mv, mkdir, rm),
with the GNU Makefile (make) and with a text editor for source coding is therefore assumed.
Sample scripts sample/.bashrc and sample/.cshrc for Linux, as well as sample/login.bat for Windows are also provided to
support both sh/bash and csh/tcsh Linux shells and the Windows Command Prompt.
Detailed step-by-step instructions are provided in form of a "lab zero" to help students to setup a suitable development environment for both Linux and Windows operating systems.
NOTE
The number of Linux shell commands used through the course is very small indeed. If you are unfamiliar to work with the Linux command line a complete list of basic commands used in the course can be reviewed here.
An endless number of online tutorials and examples is available otherwise, just search for "Linux basic commands" or similar.
As an example:
During the course we will write and discuss a lot of source code in form of plain-text files (VHDL sources, XDC constraints, Tcl scripts, GNU Makefiles etc.).
These sources are tracked using the Git versioning tool. All students are therefore requested to have a working Git installation to clone the repository and get updates.
Usually git is already installed by default on most Linux distributions. Verify that git is found in your search path with:
% which git
In case the Git package is not installed on your Linux system, use
% sudo yum install git
or
% sudo apt-get install git
according to the package manager of the Linux distribution you are working with.
Students working on a Windows system can download and install Git for Windows from the project official page:
Detailed instructions for the installation can be found here.
Before starting to use git you are requested to do some initial configuration as follows:
% git config --global user.name "Your Name"
% git config --global user.email your.email@example.com
These settings are internal to Git and local to your machine. For the email address you can use
your official name.surname@edu.unito.it address. You can then check your configuration at any time with:
% git config --list
All students are requested to use git from the command-line to download the repository and to keep track of updates.
In order to download the repository for the first time open a terminal and type:
% cd Desktop
% git clone https://github.com/lpacher/fphd.git [optional target directory]
By default a new fphd/ directory containing the repository will be created where you invoked the above git command, unless
you specify a different target directory as optional parameter.
Feel free to use a different target directory. As an example:
% cd Desktop/Documents
% git clone https://github.com/lpacher/fphd.git FPGA
IMPORTANT !
All cut-and-paste instructions in
READMEfiles assume that you clone the repository asfphdon your Desktop. If you decide to clone the repository either with a different name or into a different location it will be up to you to properly change the path to the repository wherever required.
According to Git jargon, the first time you download the repository you are in the master branch.
The master branch should always represent the "stable version" of the project:
% cd Desktop/fphd
% git branch
*master
The asterisk indicates the current working branch.
As a first step after downloading the repository for the first time you are requested to
create your personal development branch named student as follows:
% git branch student
% git checkout student
You can now list all branches in your local machine with:
% git branch
master
*student
Please, be sure that the asterisk now points to your own development branch student and not to the master branch.
Each time you will need to update your local copy of the repository simply perform a pull from the remote repository using:
% git pull origin master
IMPORTANT !
All
gitcommands must be invoked inside the topfphd/directory or from any other sub-directory of the repository!
In this course students are only requested to use git to "clone" the repository for the first time and then to "pull" from the master branch
to get updates whenever required.
If you are interested in using Git for other projects a small collection of the most frequently used git command-line syntax for your
day-to-day work and common tasks can be found here.
A more complete guide to the basic git commands can be found here.
A small mixed-language HDL design example is provided to help students in testing
their overall command-line environment setup and all software installations required for the course.
Step-by-step instructions explaining how to run this test flow can be found here.
NOTE
Links to Xilinx official documentation refer to Vivado version 2019.2 !
Digital electronics and logic design fundamentals
- J.D. Daniels, Digital Design from Zero to One
- J.F. Wakerly, Digital Design Principles and Practices
- A.K. Maini, Digital Electronics, Principles, Devices and Applications
- M.M. Mano and C.R. Kime, Logic and Computer Design Fundamentals
VHDL programming
- B. Mealy and F. Tappero, Free Range VHDL (open source)
- C.H. Roth Jr, Digital Systems Design Using VHDL
- V.A. Pedroni, Circuit Design with VHDL
- R.E. Haskell and D.M. Hanna, Introduction to Digital Design Using Digilent FPGA Boards / VHDL Examples
- P.P. Chu, FPGA Prototyping By VHDL Examples
- M. Field, Introducing the Spartan 3E FPGA and VHDL (open source)
- P. Ashenden, The Designer's Guide to VHDL
Verilog programming
- Z. Navabi, Verilog Digital System Design
- D.E. Thomas and P.R. Moorby, The Verilog Hardware Description Language
- R.E. Haskell and D.M. Hanna, Introduction to Digital Design Using Digilent FPGA Boards / Verilog Examples
- F. Vahid, Verilog for Digital Design
- P.P. Chu, FPGA Prototyping By Verilog Examples
FPGA programming (mainly using Xilinx Vivado but not only)
- S. Churiwala (Editor), Designing with Xilinx FPGAs Using Vivado
- C. Unsalan and B. Tar, Digital System Design with FPGA: Implementation Using Verilog and VHDL
- R.E. Haskell and D.M. Hanna, Introduction to Digital Design Using Digilent FPGA Boards / Verilog (VHDL) Vivado Edition
- S. Kilts, Advanced FPGA Design: Architecture, Implementation, and Optimization
- E. Stavinov, 100 Power Tips for FPGA Designers
- C. Maxfield, The Design Warrior's Guide to FPGAs: Devices, Tools and Flows
Xilinx Vivado official documentation (open)
- Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973)
- Vivado Design Suite User Guide: Getting Started (UG910)
- Vivado Design Suite User Guide: Design Flows Overview (UG892)
- Vivado Design Suite User Guide: Using the Vivado IDE (UG893)
- Vivado Design Suite User Guide: Using Tcl Scripting (UG894)
- Vivado Design Suite User Guide: System-Level Design Entry (UG895)
- Vivado Design Suite User Guide: Designing with IP (UG896)
- Vivado Design Suite User Guide: Model-Based DSP Design Using System Generator (UG897)
- Vivado Design Suite User Guide: Embedded Processor Hardware Design (UG898)
- Vivado Design Suite User Guide: I/O and Clock Planning (UG899)
- Vivado Design Suite User Guide: Logic Simulation (UG900)
- Vivado Design Suite User Guide: Synthesis (UG901)
- Vivado Design Suite User Guide: High-Level Synthesis (UG902)
- Vivado Design Suite User Guide: Using Constraints (UG903)
- Vivado Design Suite User Guide: Implementation (UG904)
- Vivado Design Suite User Guide: Hierarchical Design (UG905)
- Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)
- Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)
- Vivado Design Suite User Guide: Programming and Debugging (UG908)
- Vivado Design Suite User Guide: Partial Reconfiguration (UG909)
- UltraFast Design Methodology Guide for the Vivado Design Suite (UG949)
Xilinx 7-series FPGAs official documentation (open)
- 7 Series FPGAs Data Sheet: Overview (DS180)
- 7 Series Product Selection Guide
- 7 Series FPGAs Configuration User Guide (UG470)
- 7 Series FPGAs SelectIO Resources User Guide (UG471)
- 7 Series FPGAs Clocking Resources User Guide (UG472)
- 7 Series FPGAs Memory Resources User Guide (UG473)
- 7 Series FPGAs Configurable Logic Block User Guide (UG474)
- 7 Series FPGAs Packaging and Pinout User Guide (UG475)
- 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476)
- 7 Series FPGAs DSP48E1 Slice User Guide (UG479)
- 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter
User Guide (UG480) - 7 Series FPGAs PCB Design Guide (UG483)
Design constraints
- S. Gangadaran and S. Churiwala, Constraining Designs for Synthesis and Timing
Analysis: A Practical Guide to Synopsys Design Constraints (SDC) - Vivado Design Suite User Guide: Using Constraints (UG903)
- Vivado Design Suite Tutorial: Using Constraints (UG945)
Tcl programming
- B.B. Welch, Practical Programming in Tcl and Tk
- J.K. Ousterhout, Tcl and the Tk Toolkit
- A.P. Nadkarni, The Tcl Programming Language: A Comprehensive Guide
- Vivado Design Suite Tcl Command Reference Guide (UG835)
- Vivado Design Suite User Guide: Using Tcl Scripting (UG894)
- TCL/TK Command Reference Guide
- TCL/TK Quick Reference Card
- https://www.fpga4student.com
- https://www.fpga4fun.com
- http://www.asic-world.com/verilog/index.html
- http://www.asic-world.com/vhdl/index.html
- https://www.nandland.com/verilog/tutorials/index.html
- https://www.nandland.com/vhdl/tutorials/index.html
- https://vhdlwhiz.com/basic-vhdl-tutorials
- https://en.wikibooks.org/wiki/Category:Book:VHDL_for_FPGA_Design
- https://surf-vhdl.com
- https://www.so-logic.net/documents/knowledge/tutorial/Basic_FPGA_Tutorial_VHDL
- https://www.hackster.io/xilinx/projects
- https://web.archive.org/web/20190115230224/http://hamsterworks.co.nz/mediawiki/index.php/FPGA_Projects
- https://www.01signal.com (very nice and complete blog about FPGA design)
A list of of common acronyms and abbreviations relevant to electronics engineering and FPGA programming
can be found here.
In order to maximize the participation all lectures will be held remotely using the WebEx UniTO platform.
All lectures will be also video-recorded.
The virtual room to attend the lectures is accessible at the following link:
https://unito.webex.com/meet/luca.pacher
The complete list of past video-recorded lectures can be accessed here.
-
Lecture 1
https://unito.webex.com/recordingservice/sites/unito/recording/play/f5510ecef7c0103bafec5ed50d23eeac -
Lecture 2
https://unito.webex.com/recordingservice/sites/unito/recording/play/48a338f0f88a103bbf7cd620c2ef7930 -
Lecture 3
https://unito.webex.com/recordingservice/sites/unito/recording/play/3712f84df953103bb9fb6a1108ce59c9 -
Lecture 4
https://unito.webex.com/recordingservice/sites/unito/recording/play/00f87711fbaf103bb95f6a1108ce59c9 -
Lecture 5
https://unito.webex.com/recordingservice/sites/unito/recording/play/0431b746fc78103bbff7ae3bcd3007a7 -
Lecture 6
https://unito.webex.com/recordingservice/sites/unito/recording/play/2dfffb53fd41103ba7ff7a88bbff909e -
Lecture 7
https://unito.webex.com/recordingservice/sites/unito/recording/play/719d3471fed3103bb99d3ed1083c320c -
Lecture 8
https://unito.webex.com/recordingservice/sites/unito/recording/play/ce1d9d3f012e103cbf7e162619a3ba71
No extra lectures.