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usb1286def.inc
executable file
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usb1286def.inc
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;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
;***** Created: 2011-02-09 12:03 ******* Source: AT90USB1286.xml *********
;*************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number : AVR000
;* File Name : "usb1286def.inc"
;* Title : Register/Bit Definitions for the AT90USB1286
;* Date : 2011-02-09
;* Version : 2.35
;* Support E-mail : avr@atmel.com
;* Target MCU : AT90USB1286
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;* The Register names are represented by their hexadecimal address.
;*
;* The Register Bit names are represented by their bit number (0-7).
;*
;* Please observe the difference in using the bit names with instructions
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
;* (skip if bit in register set/cleared). The following example illustrates
;* this:
;*
;* in r16,PORTB ;read PORTB latch
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
;* out PORTB,r16 ;output to PORTB
;*
;* in r16,TIFR ;read the Timer Interrupt Flag Register
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
;* rjmp TOV0_is_set ;jump if set
;* ... ;otherwise do something else
;*************************************************************************
#ifndef _USB1286DEF_INC_
#define _USB1286DEF_INC_
#pragma partinc 0
; ***** SPECIFY DEVICE ***************************************************
.device AT90USB1286
#pragma AVRPART ADMIN PART_NAME AT90USB1286
.equ SIGNATURE_000 = 0x1e
.equ SIGNATURE_001 = 0x97
.equ SIGNATURE_002 = 0x82
#pragma AVRPART CORE CORE_VERSION V3
; ***** I/O REGISTER DEFINITIONS *****************************************
; NOTE:
; Definitions marked "MEMORY MAPPED"are extended I/O ports
; and cannot be used with IN/OUT instructions
.equ PLLCSR = 0x29
.equ TESTPADSTATUS = 0xfd ; MEMORY MAPPED
.equ TESTPADPULL = 0xfe ; MEMORY MAPPED
.equ TESTPADCTRL = 0xff ; MEMORY MAPPED
.equ UPERRX = 0xf5 ; MEMORY MAPPED
.equ UEINT = 0xf4 ; MEMORY MAPPED
.equ UPINT = 0xf8 ; MEMORY MAPPED
.equ UEBCHX = 0xf3 ; MEMORY MAPPED
.equ UPBCHX = 0xf7 ; MEMORY MAPPED
.equ UEBCLX = 0xf2 ; MEMORY MAPPED
.equ UPBCLX = 0xf6 ; MEMORY MAPPED
.equ UEDATX = 0xf1 ; MEMORY MAPPED
.equ UPDATX = 0xaf ; MEMORY MAPPED
.equ UEIENX = 0xf0 ; MEMORY MAPPED
.equ UPIENX = 0xae ; MEMORY MAPPED
.equ UESTA1X = 0xef ; MEMORY MAPPED
.equ UPCFG2X = 0xad ; MEMORY MAPPED
.equ UESTA0X = 0xee ; MEMORY MAPPED
.equ UPSTAX = 0xac ; MEMORY MAPPED
.equ UECFG1X = 0xed ; MEMORY MAPPED
.equ UPCFG1X = 0xab ; MEMORY MAPPED
.equ UECFG0X = 0xec ; MEMORY MAPPED
.equ UPCFG0X = 0xaa ; MEMORY MAPPED
.equ UECONX = 0xeb ; MEMORY MAPPED
.equ UPCONX = 0xa9 ; MEMORY MAPPED
.equ UERST = 0xea ; MEMORY MAPPED
.equ UPRST = 0xa8 ; MEMORY MAPPED
.equ UENUM = 0xe9 ; MEMORY MAPPED
.equ UPNUM = 0xa7 ; MEMORY MAPPED
.equ UEINTX = 0xe8 ; MEMORY MAPPED
.equ UPINTX = 0xa6 ; MEMORY MAPPED
.equ UDTST = 0xe7 ; MEMORY MAPPED
.equ UPINRQX = 0xa5 ; MEMORY MAPPED
.equ UDMFN = 0xe6 ; MEMORY MAPPED
.equ UHFLEN = 0xa4 ; MEMORY MAPPED
.equ UDFNUMH = 0xe5 ; MEMORY MAPPED
.equ UHFNUMH = 0xa3 ; MEMORY MAPPED
.equ UDFNUML = 0xe4 ; MEMORY MAPPED
.equ UHFNUML = 0xa2 ; MEMORY MAPPED
.equ UDADDR = 0xe3 ; MEMORY MAPPED
.equ UHADDR = 0xa1 ; MEMORY MAPPED
.equ UDIEN = 0xe2 ; MEMORY MAPPED
.equ UHIEN = 0xa0 ; MEMORY MAPPED
.equ UDINT = 0xe1 ; MEMORY MAPPED
.equ UHINT = 0x9f ; MEMORY MAPPED
.equ UDCON = 0xe0 ; MEMORY MAPPED
.equ UHCON = 0x9e ; MEMORY MAPPED
.equ OTGINT = 0xdf ; MEMORY MAPPED
.equ OTGIEN = 0xde ; MEMORY MAPPED
.equ OTGCON = 0xdd ; MEMORY MAPPED
.equ OTGTCON = 0xf9 ; MEMORY MAPPED
.equ USBINT = 0xda ; MEMORY MAPPED
.equ USBSTA = 0xd9 ; MEMORY MAPPED
.equ USBCON = 0xd8 ; MEMORY MAPPED
.equ UHWCON = 0xd7 ; MEMORY MAPPED
.equ UDR1 = 0xce ; MEMORY MAPPED
.equ UBRR1L = 0xcc ; MEMORY MAPPED
.equ UBRR1H = 0xcd ; MEMORY MAPPED
.equ UCSR1C = 0xca ; MEMORY MAPPED
.equ UCSR1B = 0xc9 ; MEMORY MAPPED
.equ UCSR1A = 0xc8 ; MEMORY MAPPED
.equ TWAMR = 0xbd ; MEMORY MAPPED
.equ TWCR = 0xbc ; MEMORY MAPPED
.equ TWDR = 0xbb ; MEMORY MAPPED
.equ TWAR = 0xba ; MEMORY MAPPED
.equ TWSR = 0xb9 ; MEMORY MAPPED
.equ TWBR = 0xb8 ; MEMORY MAPPED
.equ ASSR = 0xb6 ; MEMORY MAPPED
.equ OCR2B = 0xb4 ; MEMORY MAPPED
.equ OCR2A = 0xb3 ; MEMORY MAPPED
.equ TCNT2 = 0xb2 ; MEMORY MAPPED
.equ TCCR2B = 0xb1 ; MEMORY MAPPED
.equ TCCR2A = 0xb0 ; MEMORY MAPPED
.equ OCR3CL = 0x9c ; MEMORY MAPPED
.equ OCR3CH = 0x9d ; MEMORY MAPPED
.equ OCR3BL = 0x9a ; MEMORY MAPPED
.equ OCR3BH = 0x9b ; MEMORY MAPPED
.equ OCR3AL = 0x98 ; MEMORY MAPPED
.equ OCR3AH = 0x99 ; MEMORY MAPPED
.equ ICR3L = 0x96 ; MEMORY MAPPED
.equ ICR3H = 0x97 ; MEMORY MAPPED
.equ TCNT3L = 0x94 ; MEMORY MAPPED
.equ TCNT3H = 0x95 ; MEMORY MAPPED
.equ TCCR3C = 0x92 ; MEMORY MAPPED
.equ TCCR3B = 0x91 ; MEMORY MAPPED
.equ TCCR3A = 0x90 ; MEMORY MAPPED
.equ OCR1CL = 0x8c ; MEMORY MAPPED
.equ OCR1CH = 0x8d ; MEMORY MAPPED
.equ OCR1BL = 0x8a ; MEMORY MAPPED
.equ OCR1BH = 0x8b ; MEMORY MAPPED
.equ OCR1AL = 0x88 ; MEMORY MAPPED
.equ OCR1AH = 0x89 ; MEMORY MAPPED
.equ ICR1L = 0x86 ; MEMORY MAPPED
.equ ICR1H = 0x87 ; MEMORY MAPPED
.equ TCNT1L = 0x84 ; MEMORY MAPPED
.equ TCNT1H = 0x85 ; MEMORY MAPPED
.equ TCCR1C = 0x82 ; MEMORY MAPPED
.equ TCCR1B = 0x81 ; MEMORY MAPPED
.equ TCCR1A = 0x80 ; MEMORY MAPPED
.equ DIDR1 = 0x7f ; MEMORY MAPPED
.equ DIDR0 = 0x7e ; MEMORY MAPPED
.equ DIDR2 = 0x7d ; MEMORY MAPPED
.equ ADMUX = 0x7c ; MEMORY MAPPED
.equ ADCSRB = 0x7b ; MEMORY MAPPED
.equ ADCSRA = 0x7a ; MEMORY MAPPED
.equ ADCH = 0x79 ; MEMORY MAPPED
.equ ADCL = 0x78 ; MEMORY MAPPED
.equ XMCRB = 0x75 ; MEMORY MAPPED
.equ XMCRA = 0x74 ; MEMORY MAPPED
.equ TIMSK5 = 0x73 ; MEMORY MAPPED
.equ TIMSK4 = 0x72 ; MEMORY MAPPED
.equ TIMSK3 = 0x71 ; MEMORY MAPPED
.equ TIMSK2 = 0x70 ; MEMORY MAPPED
.equ TIMSK1 = 0x6f ; MEMORY MAPPED
.equ TIMSK0 = 0x6e ; MEMORY MAPPED
.equ PCMSK2 = 0x6d ; MEMORY MAPPED
.equ PCMSK1 = 0x6c ; MEMORY MAPPED
.equ PCMSK0 = 0x6b ; MEMORY MAPPED
.equ EICRB = 0x6a ; MEMORY MAPPED
.equ EICRA = 0x69 ; MEMORY MAPPED
.equ PCICR = 0x68 ; MEMORY MAPPED
.equ OSCCAL = 0x66 ; MEMORY MAPPED
.equ PRR1 = 0x65 ; MEMORY MAPPED
.equ PRR0 = 0x64 ; MEMORY MAPPED
.equ CLKPR = 0x61 ; MEMORY MAPPED
.equ WDTCSR = 0x60 ; MEMORY MAPPED
.equ SREG = 0x3f
.equ SPL = 0x3d
.equ SPH = 0x3e
.equ EIND = 0x3c
.equ RAMPZ = 0x3b
.equ SPMCSR = 0x37
.equ MCUCR = 0x35
.equ MCUSR = 0x34
.equ SMCR = 0x33
.equ OCDR = 0x31
.equ ACSR = 0x30
.equ SPDR = 0x2e
.equ SPSR = 0x2d
.equ SPCR = 0x2c
.equ GPIOR2 = 0x2b
.equ GPIOR1 = 0x2a
.equ OCR0B = 0x28
.equ OCR0A = 0x27
.equ TCNT0 = 0x26
.equ TCCR0B = 0x25
.equ TCCR0A = 0x24
.equ GTCCR = 0x23
.equ EEARH = 0x22
.equ EEARL = 0x21
.equ EEDR = 0x20
.equ EECR = 0x1f
.equ GPIOR0 = 0x1e
.equ EIMSK = 0x1d
.equ EIFR = 0x1c
.equ PCIFR = 0x1b
.equ TIFR5 = 0x1a
.equ TIFR4 = 0x19
.equ TIFR3 = 0x18
.equ TIFR2 = 0x17
.equ TIFR1 = 0x16
.equ TIFR0 = 0x15
.equ PORTF = 0x11
.equ DDRF = 0x10
.equ PINF = 0x0f
.equ PORTE = 0x0e
.equ DDRE = 0x0d
.equ PINE = 0x0c
.equ PORTD = 0x0b
.equ DDRD = 0x0a
.equ PIND = 0x09
.equ PORTC = 0x08
.equ DDRC = 0x07
.equ PINC = 0x06
.equ PORTB = 0x05
.equ DDRB = 0x04
.equ PINB = 0x03
.equ PORTA = 0x02
.equ DDRA = 0x01
.equ PINA = 0x00
; ***** BIT DEFINITIONS **************************************************
; ***** WATCHDOG *********************
; WDTCSR - Watchdog Timer Control Register
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
.equ WDE = 3 ; Watch Dog Enable
.equ WDCE = 4 ; Watchdog Change Enable
.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3
.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable
.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag
; ***** PORTA ************************
; PORTA - Port A Data Register
.equ PORTA0 = 0 ; Port A Data Register bit 0
.equ PA0 = 0 ; For compatibility
.equ PORTA1 = 1 ; Port A Data Register bit 1
.equ PA1 = 1 ; For compatibility
.equ PORTA2 = 2 ; Port A Data Register bit 2
.equ PA2 = 2 ; For compatibility
.equ PORTA3 = 3 ; Port A Data Register bit 3
.equ PA3 = 3 ; For compatibility
.equ PORTA4 = 4 ; Port A Data Register bit 4
.equ PA4 = 4 ; For compatibility
.equ PORTA5 = 5 ; Port A Data Register bit 5
.equ PA5 = 5 ; For compatibility
.equ PORTA6 = 6 ; Port A Data Register bit 6
.equ PA6 = 6 ; For compatibility
.equ PORTA7 = 7 ; Port A Data Register bit 7
.equ PA7 = 7 ; For compatibility
; DDRA - Port A Data Direction Register
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7
; PINA - Port A Input Pins
.equ PINA0 = 0 ; Input Pins, Port A bit 0
.equ PINA1 = 1 ; Input Pins, Port A bit 1
.equ PINA2 = 2 ; Input Pins, Port A bit 2
.equ PINA3 = 3 ; Input Pins, Port A bit 3
.equ PINA4 = 4 ; Input Pins, Port A bit 4
.equ PINA5 = 5 ; Input Pins, Port A bit 5
.equ PINA6 = 6 ; Input Pins, Port A bit 6
.equ PINA7 = 7 ; Input Pins, Port A bit 7
; ***** PORTB ************************
; PORTB - Port B Data Register
.equ PORTB0 = 0 ; Port B Data Register bit 0
.equ PB0 = 0 ; For compatibility
.equ PORTB1 = 1 ; Port B Data Register bit 1
.equ PB1 = 1 ; For compatibility
.equ PORTB2 = 2 ; Port B Data Register bit 2
.equ PB2 = 2 ; For compatibility
.equ PORTB3 = 3 ; Port B Data Register bit 3
.equ PB3 = 3 ; For compatibility
.equ PORTB4 = 4 ; Port B Data Register bit 4
.equ PB4 = 4 ; For compatibility
.equ PORTB5 = 5 ; Port B Data Register bit 5
.equ PB5 = 5 ; For compatibility
.equ PORTB6 = 6 ; Port B Data Register bit 6
.equ PB6 = 6 ; For compatibility
.equ PORTB7 = 7 ; Port B Data Register bit 7
.equ PB7 = 7 ; For compatibility
; DDRB - Port B Data Direction Register
.equ DDB0 = 0 ; Port B Data Direction Register bit 0
.equ DDB1 = 1 ; Port B Data Direction Register bit 1
.equ DDB2 = 2 ; Port B Data Direction Register bit 2
.equ DDB3 = 3 ; Port B Data Direction Register bit 3
.equ DDB4 = 4 ; Port B Data Direction Register bit 4
.equ DDB5 = 5 ; Port B Data Direction Register bit 5
.equ DDB6 = 6 ; Port B Data Direction Register bit 6
.equ DDB7 = 7 ; Port B Data Direction Register bit 7
; PINB - Port B Input Pins
.equ PINB0 = 0 ; Port B Input Pins bit 0
.equ PINB1 = 1 ; Port B Input Pins bit 1
.equ PINB2 = 2 ; Port B Input Pins bit 2
.equ PINB3 = 3 ; Port B Input Pins bit 3
.equ PINB4 = 4 ; Port B Input Pins bit 4
.equ PINB5 = 5 ; Port B Input Pins bit 5
.equ PINB6 = 6 ; Port B Input Pins bit 6
.equ PINB7 = 7 ; Port B Input Pins bit 7
; ***** PORTC ************************
; PORTC - Port C Data Register
.equ PORTC0 = 0 ; Port C Data Register bit 0
.equ PC0 = 0 ; For compatibility
.equ PORTC1 = 1 ; Port C Data Register bit 1
.equ PC1 = 1 ; For compatibility
.equ PORTC2 = 2 ; Port C Data Register bit 2
.equ PC2 = 2 ; For compatibility
.equ PORTC3 = 3 ; Port C Data Register bit 3
.equ PC3 = 3 ; For compatibility
.equ PORTC4 = 4 ; Port C Data Register bit 4
.equ PC4 = 4 ; For compatibility
.equ PORTC5 = 5 ; Port C Data Register bit 5
.equ PC5 = 5 ; For compatibility
.equ PORTC6 = 6 ; Port C Data Register bit 6
.equ PC6 = 6 ; For compatibility
.equ PORTC7 = 7 ; Port C Data Register bit 7
.equ PC7 = 7 ; For compatibility
; DDRC - Port C Data Direction Register
.equ DDC0 = 0 ; Port C Data Direction Register bit 0
.equ DDC1 = 1 ; Port C Data Direction Register bit 1
.equ DDC2 = 2 ; Port C Data Direction Register bit 2
.equ DDC3 = 3 ; Port C Data Direction Register bit 3
.equ DDC4 = 4 ; Port C Data Direction Register bit 4
.equ DDC5 = 5 ; Port C Data Direction Register bit 5
.equ DDC6 = 6 ; Port C Data Direction Register bit 6
.equ DDC7 = 7 ; Port C Data Direction Register bit 7
; PINC - Port C Input Pins
.equ PINC0 = 0 ; Port C Input Pins bit 0
.equ PINC1 = 1 ; Port C Input Pins bit 1
.equ PINC2 = 2 ; Port C Input Pins bit 2
.equ PINC3 = 3 ; Port C Input Pins bit 3
.equ PINC4 = 4 ; Port C Input Pins bit 4
.equ PINC5 = 5 ; Port C Input Pins bit 5
.equ PINC6 = 6 ; Port C Input Pins bit 6
.equ PINC7 = 7 ; Port C Input Pins bit 7
; ***** PORTD ************************
; PORTD - Port D Data Register
.equ PORTD0 = 0 ; Port D Data Register bit 0
.equ PD0 = 0 ; For compatibility
.equ PORTD1 = 1 ; Port D Data Register bit 1
.equ PD1 = 1 ; For compatibility
.equ PORTD2 = 2 ; Port D Data Register bit 2
.equ PD2 = 2 ; For compatibility
.equ PORTD3 = 3 ; Port D Data Register bit 3
.equ PD3 = 3 ; For compatibility
.equ PORTD4 = 4 ; Port D Data Register bit 4
.equ PD4 = 4 ; For compatibility
.equ PORTD5 = 5 ; Port D Data Register bit 5
.equ PD5 = 5 ; For compatibility
.equ PORTD6 = 6 ; Port D Data Register bit 6
.equ PD6 = 6 ; For compatibility
.equ PORTD7 = 7 ; Port D Data Register bit 7
.equ PD7 = 7 ; For compatibility
; DDRD - Port D Data Direction Register
.equ DDD0 = 0 ; Port D Data Direction Register bit 0
.equ DDD1 = 1 ; Port D Data Direction Register bit 1
.equ DDD2 = 2 ; Port D Data Direction Register bit 2
.equ DDD3 = 3 ; Port D Data Direction Register bit 3
.equ DDD4 = 4 ; Port D Data Direction Register bit 4
.equ DDD5 = 5 ; Port D Data Direction Register bit 5
.equ DDD6 = 6 ; Port D Data Direction Register bit 6
.equ DDD7 = 7 ; Port D Data Direction Register bit 7
; PIND - Port D Input Pins
.equ PIND0 = 0 ; Port D Input Pins bit 0
.equ PIND1 = 1 ; Port D Input Pins bit 1
.equ PIND2 = 2 ; Port D Input Pins bit 2
.equ PIND3 = 3 ; Port D Input Pins bit 3
.equ PIND4 = 4 ; Port D Input Pins bit 4
.equ PIND5 = 5 ; Port D Input Pins bit 5
.equ PIND6 = 6 ; Port D Input Pins bit 6
.equ PIND7 = 7 ; Port D Input Pins bit 7
; ***** PORTE ************************
; PORTE - Data Register, Port E
.equ PORTE0 = 0 ;
.equ PE0 = 0 ; For compatibility
.equ PORTE1 = 1 ;
.equ PE1 = 1 ; For compatibility
.equ PORTE2 = 2 ;
.equ PE2 = 2 ; For compatibility
.equ PORTE3 = 3 ;
.equ PE3 = 3 ; For compatibility
.equ PORTE4 = 4 ;
.equ PE4 = 4 ; For compatibility
.equ PORTE5 = 5 ;
.equ PE5 = 5 ; For compatibility
.equ PORTE6 = 6 ;
.equ PE6 = 6 ; For compatibility
.equ PORTE7 = 7 ;
.equ PE7 = 7 ; For compatibility
; DDRE - Data Direction Register, Port E
.equ DDE0 = 0 ;
.equ DDE1 = 1 ;
.equ DDE2 = 2 ;
.equ DDE3 = 3 ;
.equ DDE4 = 4 ;
.equ DDE5 = 5 ;
.equ DDE6 = 6 ;
.equ DDE7 = 7 ;
; PINE - Input Pins, Port E
.equ PINE0 = 0 ;
.equ PINE1 = 1 ;
.equ PINE2 = 2 ;
.equ PINE3 = 3 ;
.equ PINE4 = 4 ;
.equ PINE5 = 5 ;
.equ PINE6 = 6 ;
.equ PINE7 = 7 ;
; ***** PORTF ************************
; PORTF - Data Register, Port F
.equ PORTF0 = 0 ;
.equ PF0 = 0 ; For compatibility
.equ PORTF1 = 1 ;
.equ PF1 = 1 ; For compatibility
.equ PORTF2 = 2 ;
.equ PF2 = 2 ; For compatibility
.equ PORTF3 = 3 ;
.equ PF3 = 3 ; For compatibility
.equ PORTF4 = 4 ;
.equ PF4 = 4 ; For compatibility
.equ PORTF5 = 5 ;
.equ PF5 = 5 ; For compatibility
.equ PORTF6 = 6 ;
.equ PF6 = 6 ; For compatibility
.equ PORTF7 = 7 ;
.equ PF7 = 7 ; For compatibility
; DDRF - Data Direction Register, Port F
.equ DDF0 = 0 ;
.equ DDF1 = 1 ;
.equ DDF2 = 2 ;
.equ DDF3 = 3 ;
.equ DDF4 = 4 ;
.equ DDF5 = 5 ;
.equ DDF6 = 6 ;
.equ DDF7 = 7 ;
; PINF - Input Pins, Port F
.equ PINF0 = 0 ;
.equ PINF1 = 1 ;
.equ PINF2 = 2 ;
.equ PINF3 = 3 ;
.equ PINF4 = 4 ;
.equ PINF5 = 5 ;
.equ PINF6 = 6 ;
.equ PINF7 = 7 ;
; ***** CPU **************************
; SREG - Status Register
.equ SREG_C = 0 ; Carry Flag
.equ SREG_Z = 1 ; Zero Flag
.equ SREG_N = 2 ; Negative Flag
.equ SREG_V = 3 ; Two's Complement Overflow Flag
.equ SREG_S = 4 ; Sign Bit
.equ SREG_H = 5 ; Half Carry Flag
.equ SREG_T = 6 ; Bit Copy Storage
.equ SREG_I = 7 ; Global Interrupt Enable
; MCUCR - MCU Control Register
.equ IVCE = 0 ; Interrupt Vector Change Enable
.equ IVSEL = 1 ; Interrupt Vector Select
.equ PUD = 4 ; Pull-up disable
.equ JTD = 7 ; JTAG Interface Disable
; MCUSR - MCU Status Register
.equ PORF = 0 ; Power-on reset flag
.equ EXTRF = 1 ; External Reset Flag
.equ BORF = 2 ; Brown-out Reset Flag
.equ WDRF = 3 ; Watchdog Reset Flag
.equ JTRF = 4 ; JTAG Reset Flag
; XMCRA - External Memory Control Register A
.equ SRW00 = 0 ; Wait state select bit lower page
.equ SRW01 = 1 ; Wait state select bit lower page
.equ SRW10 = 2 ; Wait state select bit upper page
.equ SRW11 = 3 ; Wait state select bit upper page
.equ SRL0 = 4 ; Wait state page limit
.equ SRL1 = 5 ; Wait state page limit
.equ SRL2 = 6 ; Wait state page limit
.equ SRE = 7 ; External SRAM Enable
; XMCRB - External Memory Control Register B
.equ XMM0 = 0 ; External Memory High Mask
.equ XMM1 = 1 ; External Memory High Mask
.equ XMM2 = 2 ; External Memory High Mask
.equ XMBK = 7 ; External Memory Bus Keeper Enable
; OSCCAL - Oscillator Calibration Value
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6
.equ CAL7 = 7 ; Oscillator Calibration Value Bit7
; CLKPR -
.equ CLKPS0 = 0 ;
.equ CLKPS1 = 1 ;
.equ CLKPS2 = 2 ;
.equ CLKPS3 = 3 ;
.equ CLKPCE = 7 ;
; SMCR - Sleep Mode Control Register
.equ SE = 0 ; Sleep Enable
.equ SM0 = 1 ; Sleep Mode Select bit 0
.equ SM1 = 2 ; Sleep Mode Select bit 1
.equ SM2 = 3 ; Sleep Mode Select bit 2
; RAMPZ - RAM Page Z Select Register
.equ RAMPZ0 = 0 ; RAM Page Z Select Register Bit 0
; EIND - Extended Indirect Register
.equ EIND0 = 0 ; Bit 0
; GPIOR2 - General Purpose IO Register 2
.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0
.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1
.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2
.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3
.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4
.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5
.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6
.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7
; GPIOR1 - General Purpose IO Register 1
.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0
.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1
.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2
.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3
.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4
.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5
.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6
.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7
; GPIOR0 - General Purpose IO Register 0
.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0
.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1
.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2
.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3
.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4
.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5
.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6
.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7
; PRR1 - Power Reduction Register1
.equ PRUSART1 = 0 ; Power Reduction USART1
.equ PRTIM3 = 3 ; Power Reduction Timer/Counter3
.equ PRUSB = 7 ; Power Reduction USB
; PRR0 - Power Reduction Register0
.equ PRADC = 0 ; Power Reduction ADC
.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface
.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1
.equ PRTIM0 = 5 ; Power Reduction Timer/Counter0
.equ PRTIM2 = 6 ; Power Reduction Timer/Counter2
.equ PRTWI = 7 ; Power Reduction TWI
; ***** TWI **************************
; TWAMR - TWI (Slave) Address Mask Register
.equ TWAM0 = 1 ;
.equ TWAMR0 = TWAM0 ; For compatibility
.equ TWAM1 = 2 ;
.equ TWAMR1 = TWAM1 ; For compatibility
.equ TWAM2 = 3 ;
.equ TWAMR2 = TWAM2 ; For compatibility
.equ TWAM3 = 4 ;
.equ TWAMR3 = TWAM3 ; For compatibility
.equ TWAM4 = 5 ;
.equ TWAMR4 = TWAM4 ; For compatibility
.equ TWAM5 = 6 ;
.equ TWAMR5 = TWAM5 ; For compatibility
.equ TWAM6 = 7 ;
.equ TWAMR6 = TWAM6 ; For compatibility
; TWBR - TWI Bit Rate register
.equ TWBR0 = 0 ;
.equ TWBR1 = 1 ;
.equ TWBR2 = 2 ;
.equ TWBR3 = 3 ;
.equ TWBR4 = 4 ;
.equ TWBR5 = 5 ;
.equ TWBR6 = 6 ;
.equ TWBR7 = 7 ;
; TWCR - TWI Control Register
.equ TWIE = 0 ; TWI Interrupt Enable
.equ TWEN = 2 ; TWI Enable Bit
.equ TWWC = 3 ; TWI Write Collition Flag
.equ TWSTO = 4 ; TWI Stop Condition Bit
.equ TWSTA = 5 ; TWI Start Condition Bit
.equ TWEA = 6 ; TWI Enable Acknowledge Bit
.equ TWINT = 7 ; TWI Interrupt Flag
; TWSR - TWI Status Register
.equ TWPS0 = 0 ; TWI Prescaler
.equ TWPS1 = 1 ; TWI Prescaler
.equ TWS3 = 3 ; TWI Status
.equ TWS4 = 4 ; TWI Status
.equ TWS5 = 5 ; TWI Status
.equ TWS6 = 6 ; TWI Status
.equ TWS7 = 7 ; TWI Status
; TWDR - TWI Data register
.equ TWD0 = 0 ; TWI Data Register Bit 0
.equ TWD1 = 1 ; TWI Data Register Bit 1
.equ TWD2 = 2 ; TWI Data Register Bit 2
.equ TWD3 = 3 ; TWI Data Register Bit 3
.equ TWD4 = 4 ; TWI Data Register Bit 4
.equ TWD5 = 5 ; TWI Data Register Bit 5
.equ TWD6 = 6 ; TWI Data Register Bit 6
.equ TWD7 = 7 ; TWI Data Register Bit 7
; TWAR - TWI (Slave) Address register
.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit
.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0
.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1
.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2
.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3
.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4
.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5
.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6
; ***** SPI **************************
; SPDR - SPI Data Register
.equ SPDR0 = 0 ; SPI Data Register bit 0
.equ SPDR1 = 1 ; SPI Data Register bit 1
.equ SPDR2 = 2 ; SPI Data Register bit 2
.equ SPDR3 = 3 ; SPI Data Register bit 3
.equ SPDR4 = 4 ; SPI Data Register bit 4
.equ SPDR5 = 5 ; SPI Data Register bit 5
.equ SPDR6 = 6 ; SPI Data Register bit 6
.equ SPDR7 = 7 ; SPI Data Register bit 7
; SPSR - SPI Status Register
.equ SPI2X = 0 ; Double SPI Speed Bit
.equ WCOL = 6 ; Write Collision Flag
.equ SPIF = 7 ; SPI Interrupt Flag
; SPCR - SPI Control Register
.equ SPR0 = 0 ; SPI Clock Rate Select 0
.equ SPR1 = 1 ; SPI Clock Rate Select 1
.equ CPHA = 2 ; Clock Phase
.equ CPOL = 3 ; Clock polarity
.equ MSTR = 4 ; Master/Slave Select
.equ DORD = 5 ; Data Order
.equ SPE = 6 ; SPI Enable
.equ SPIE = 7 ; SPI Interrupt Enable
; ***** USART1 ***********************
; UDR1 - USART I/O Data Register
.equ UDR1_0 = 0 ; USART I/O Data Register bit 0
.equ UDR1_1 = 1 ; USART I/O Data Register bit 1
.equ UDR1_2 = 2 ; USART I/O Data Register bit 2
.equ UDR1_3 = 3 ; USART I/O Data Register bit 3
.equ UDR1_4 = 4 ; USART I/O Data Register bit 4
.equ UDR1_5 = 5 ; USART I/O Data Register bit 5
.equ UDR1_6 = 6 ; USART I/O Data Register bit 6
.equ UDR1_7 = 7 ; USART I/O Data Register bit 7
; UCSR1A - USART Control and Status Register A
.equ MPCM1 = 0 ; Multi-processor Communication Mode
.equ U2X1 = 1 ; Double the USART transmission speed
.equ UPE1 = 2 ; Parity Error
.equ DOR1 = 3 ; Data overRun
.equ FE1 = 4 ; Framing Error
.equ UDRE1 = 5 ; USART Data Register Empty
.equ TXC1 = 6 ; USART Transmitt Complete
.equ RXC1 = 7 ; USART Receive Complete
; UCSR1B - USART Control and Status Register B
.equ TXB81 = 0 ; Transmit Data Bit 8
.equ RXB81 = 1 ; Receive Data Bit 8
.equ UCSZ12 = 2 ; Character Size
.equ TXEN1 = 3 ; Transmitter Enable
.equ RXEN1 = 4 ; Receiver Enable
.equ UDRIE1 = 5 ; USART Data register Empty Interrupt Enable
.equ TXCIE1 = 6 ; TX Complete Interrupt Enable
.equ RXCIE1 = 7 ; RX Complete Interrupt Enable
; UCSR1C - USART Control and Status Register C
.equ UCPOL1 = 0 ; Clock Polarity
.equ UCSZ10 = 1 ; Character Size
.equ UCPHA1 = UCSZ10 ; For compatibility
.equ UCSZ11 = 2 ; Character Size
.equ UDORD1 = UCSZ11 ; For compatibility
.equ USBS1 = 3 ; Stop Bit Select
.equ UPM10 = 4 ; Parity Mode Bit 0
.equ UPM11 = 5 ; Parity Mode Bit 1
.equ UMSEL10 = 6 ; USART Mode Select
.equ UMSEL11 = 7 ; USART Mode Select
; UBRR1H - USART Baud Rate Register High Byte
.equ UBRR_8 = 0 ; USART Baud Rate Register bit 8
.equ UBRR_9 = 1 ; USART Baud Rate Register bit 9
.equ UBRR_10 = 2 ; USART Baud Rate Register bit 10
.equ UBRR_11 = 3 ; USART Baud Rate Register bit 11
; UBRR1L - USART Baud Rate Register Low Byte
.equ UBRR_0 = 0 ; USART Baud Rate Register bit 0
.equ UBRR_1 = 1 ; USART Baud Rate Register bit 1
.equ UBRR_2 = 2 ; USART Baud Rate Register bit 2
.equ UBRR_3 = 3 ; USART Baud Rate Register bit 3
.equ UBRR_4 = 4 ; USART Baud Rate Register bit 4
.equ UBRR_5 = 5 ; USART Baud Rate Register bit 5
.equ UBRR_6 = 6 ; USART Baud Rate Register bit 6
.equ UBRR_7 = 7 ; USART Baud Rate Register bit 7
; ***** USB_DEVICE *******************
; UDCON -
.equ DETACH = 0 ;
.equ RMWKUP = 1 ;
.equ LSM = 2 ;
; UDINT -
.equ SUSPI = 0 ;
.equ SOFI = 2 ;
.equ EORSTI = 3 ;
.equ WAKEUPI = 4 ;
.equ EORSMI = 5 ;
.equ UPRSMI = 6 ;
; UDIEN -
.equ SUSPE = 0 ;
.equ SOFE = 2 ;
.equ EORSTE = 3 ;
.equ WAKEUPE = 4 ;
.equ EORSME = 5 ;
.equ UPRSME = 6 ;
; UDADDR -
.equ UADD0 = 0 ;
.equ UADD1 = 1 ;
.equ UADD2 = 2 ;
.equ UADD3 = 3 ;
.equ UADD4 = 4 ;
.equ UADD5 = 5 ;
.equ UADD6 = 6 ;
.equ ADDEN = 7 ;
; UDFNUML -
.equ UDFNUML_0 = 0 ;
.equ UDFNUML_1 = 1 ;
.equ UDFNUML_2 = 2 ;
.equ UDFNUML_3 = 3 ;
.equ UDFNUML_4 = 4 ;
.equ UDFNUML_5 = 5 ;
.equ UDFNUML_6 = 6 ;
.equ UDFNUML_7 = 7 ;
; UDFNUMH -
.equ UDFNUMH_0 = 0 ;
.equ UDFNUMH_1 = 1 ;
.equ UDFNUMH_2 = 2 ;
; UDMFN -
.equ FNCERR = 4 ;
; UEINTX -
.equ TXINI = 0 ;
.equ STALLEDI = 1 ;
.equ RXOUTI = 2 ;
.equ RXSTPI = 3 ;
.equ NAKOUTI = 4 ;
.equ RWAL = 5 ;
.equ NAKINI = 6 ;
.equ FIFOCON = 7 ;
; UENUM -
.equ UENUM_0 = 0 ;
.equ UENUM_1 = 1 ;
.equ UENUM_2 = 2 ;
; UERST -
.equ EPRST0 = 0 ;
.equ EPRST1 = 1 ;
.equ EPRST2 = 2 ;
.equ EPRST3 = 3 ;
.equ EPRST4 = 4 ;
.equ EPRST5 = 5 ;
.equ EPRST6 = 6 ;
; UECONX -
.equ EPEN = 0 ;
.equ RSTDT = 3 ;
.equ STALLRQC = 4 ;
.equ STALLRQ = 5 ;
; UECFG0X -
.equ EPDIR = 0 ;
.equ EPTYPE0 = 6 ;
.equ EPTYPE1 = 7 ;
; UECFG1X -
.equ ALLOC = 1 ;
.equ EPBK0 = 2 ;
.equ EPBK1 = 3 ;
.equ EPSIZE0 = 4 ;
.equ EPSIZE1 = 5 ;
.equ EPSIZE2 = 6 ;
; UESTA0X -
.equ NBUSYBK0 = 0 ;
.equ NBUSYBK1 = 1 ;
.equ DTSEQ0 = 2 ;
.equ DTSEQ1 = 3 ;
.equ UNDERFI = 5 ;
.equ OVERFI = 6 ;
.equ CFGOK = 7 ;
; UESTA1X -
.equ CURRBK0 = 0 ;
.equ CURRBK1 = 1 ;
.equ CTRLDIR = 2 ;
; UEIENX -
.equ TXINE = 0 ;
.equ STALLEDE = 1 ;
.equ RXOUTE = 2 ;
.equ RXSTPE = 3 ;
.equ NAKOUTE = 4 ;
.equ NAKINE = 6 ;
.equ FLERRE = 7 ;
; UEDATX -
.equ UEDATX_0 = 0 ;
.equ UEDATX_1 = 1 ;
.equ UEDATX_2 = 2 ;
.equ UEDATX_3 = 3 ;
.equ UEDATX_4 = 4 ;
.equ UEDATX_5 = 5 ;
.equ UEDATX_6 = 6 ;
.equ UEDATX_7 = 7 ;
; UEBCLX -
.equ UEBCLX_0 = 0 ;
.equ UEBCLX_1 = 1 ;
.equ UEBCLX_2 = 2 ;
.equ UEBCLX_3 = 3 ;
.equ UEBCLX_4 = 4 ;
.equ UEBCLX_5 = 5 ;
.equ UEBCLX_6 = 6 ;
.equ UEBCLX_7 = 7 ;
; UEBCHX -
.equ UEBCHX_0 = 0 ;
.equ UEBCHX_1 = 1 ;
.equ UEBCHX_2 = 2 ;
; UEINT -
.equ EPINT0 = 0 ;
.equ EPINT1 = 1 ;
.equ EPINT2 = 2 ;
.equ EPINT3 = 3 ;
.equ EPINT4 = 4 ;
.equ EPINT5 = 5 ;
.equ EPINT6 = 6 ;
; ***** BOOT_LOAD ********************
; SPMCSR - Store Program Memory Control Register
.equ SPMEN = 0 ; Store Program Memory Enable
.equ PGERS = 1 ; Page Erase
.equ PGWRT = 2 ; Page Write
.equ BLBSET = 3 ; Boot Lock Bit Set
.equ RWWSRE = 4 ; Read While Write section read enable
.equ SIGRD = 5 ; Signature Row Read
.equ RWWSB = 6 ; Read While Write Section Busy
.equ SPMIE = 7 ; SPM Interrupt Enable
; ***** EEPROM ***********************
; EEARH - EEPROM Address Register Low Byte
.equ EEAR8 = 0 ; EEPROM Read/Write Access Bit 8
.equ EEAR9 = 1 ; EEPROM Read/Write Access Bit 9
.equ EEAR10 = 2 ; EEPROM Read/Write Access Bit 10
.equ EEAR11 = 3 ; EEPROM Read/Write Access Bit 11
; EEARL - EEPROM Address Register Low Byte
.equ EEAR0 = 0 ; EEPROM Read/Write Access Bit 0
.equ EEAR1 = 1 ; EEPROM Read/Write Access Bit 1
.equ EEAR2 = 2 ; EEPROM Read/Write Access Bit 2
.equ EEAR3 = 3 ; EEPROM Read/Write Access Bit 3
.equ EEAR4 = 4 ; EEPROM Read/Write Access Bit 4
.equ EEAR5 = 5 ; EEPROM Read/Write Access Bit 5
.equ EEAR6 = 6 ; EEPROM Read/Write Access Bit 6
.equ EEAR7 = 7 ; EEPROM Read/Write Access Bit 7
; EEDR - EEPROM Data Register
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
; EECR - EEPROM Control Register
.equ EERE = 0 ; EEPROM Read Enable
.equ EEPE = 1 ; EEPROM Write Enable
.equ EEMPE = 2 ; EEPROM Master Write Enable
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable
.equ EEPM0 = 4 ; EEPROM Programming Mode Bit 0
.equ EEPM1 = 5 ; EEPROM Programming Mode Bit 1
; ***** TIMER_COUNTER_0 **************
; TIMSK0 - Timer/Counter0 Interrupt Mask Register
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable
.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable
; TIFR0 - Timer/Counter0 Interrupt Flag register
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0A
.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B
; TCCR0A - Timer/Counter Control Register A
.equ WGM00 = 0 ; Waveform Generation Mode
.equ WGM01 = 1 ; Waveform Generation Mode
.equ COM0B0 = 4 ; Compare Output Mode, Fast PWm
.equ COM0B1 = 5 ; Compare Output Mode, Fast PWm
.equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode
.equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode
; TCCR0B - Timer/Counter Control Register B
.equ CS00 = 0 ; Clock Select
.equ CS01 = 1 ; Clock Select
.equ CS02 = 2 ; Clock Select
.equ WGM02 = 3 ;
.equ FOC0B = 6 ; Force Output Compare B
.equ FOC0A = 7 ; Force Output Compare A
; TCNT0 - Timer/Counter0
.equ TCNT0_0 = 0 ;
.equ TCNT0_1 = 1 ;
.equ TCNT0_2 = 2 ;
.equ TCNT0_3 = 3 ;
.equ TCNT0_4 = 4 ;
.equ TCNT0_5 = 5 ;
.equ TCNT0_6 = 6 ;
.equ TCNT0_7 = 7 ;
; OCR0A - Timer/Counter0 Output Compare Register
.equ OCR0A_0 = 0 ;
.equ OCR0A_1 = 1 ;