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add special handling for AMD internal bridges, and AMD bridge missing…
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… AER
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@lprylli
lprylli committed Oct 26, 2021
1 parent 47f167e commit 1e4e870
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Showing 2 changed files with 25 additions and 22 deletions.
12 changes: 7 additions & 5 deletions cmds/pcimon/pcimon.go
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Original file line number Diff line number Diff line change
Expand Up @@ -102,10 +102,12 @@ func min(a, b int) int {
return b
}

func showLinks(world *pci.World) []*PciDev {
func showLinks(world *pci.World, aer bool) []*PciDev {
var links []*PciDev
for _, d := range world.Devs {
if d.LnkChild != nil && d.Ecap[pci.PCI_ECAP_ID_AER] > 0 && d.LnkChild.Ecap[pci.PCI_ECAP_ID_AER] > 0 {
// Exception for some AMD GPP root port not advertising AER (1022:1483), and blacklist internal pcie links (1022:1484)
upQual := (d.Ecap[pci.PCI_ECAP_ID_AER] > 0 && (d.Vendor != 0x1022 || d.Device != 0x1484)) || (!aer && d.Vendor == 0x1022 && d.Device == 0x1483)
if d.LnkChild != nil && upQual && d.LnkChild.Ecap[pci.PCI_ECAP_ID_AER] > 0 {
d.GetSpeed()
c := d.LnkChild
c.GetSpeed()
Expand All @@ -131,7 +133,7 @@ func showLinks(world *pci.World) []*PciDev {
}

func monLinks(world *pci.World, nbIter int, delayNano time.Duration) {
links := showLinks(world)
links := showLinks(world, true)
var totalErrors int64
// The LinksWithErr map records whether any error was detected for a device
// in the previous iteration (to decide whether to include it in next high-frequency poll phase)
Expand Down Expand Up @@ -281,14 +283,14 @@ func Main() {
monLinks(world, *nbIter, time.Duration(*delayOpt*1e9))
}
if *errShowOpt {
errBrowse(world, false)
errBrowse(world, true)
}

if *clearErrOpt {
errBrowse(world, true)
}
if !*monLinkOpt && !*errShowOpt && !*clearErrOpt {
showLinks(world)
showLinks(world, false)
}
}

Expand Down
35 changes: 18 additions & 17 deletions pci/defs.go
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Original file line number Diff line number Diff line change
Expand Up @@ -60,7 +60,7 @@ type BasePciDev struct {
LnkCapWidth int
downPorts int
nickname, Path string
vendor, device uint16
Vendor, Device uint16
App interface{}
}

Expand Down Expand Up @@ -121,9 +121,9 @@ func (w *World) AddDev(d *PciDev) {
d.w = w
d.reqId = d.bus*256 + d.devFn
d.devType = -1
d.vendor = d.Read16(0)
d.device = d.Read16(2)
if d.vendor == 0xffff && d.device == 0xffff {
d.Vendor = d.Read16(0)
d.Device = d.Read16(2)
if d.Vendor == 0xffff && d.Device == 0xffff {
log.Printf("%s: ignored (0xffff on id)\n", d.Name)
return
}
Expand Down Expand Up @@ -157,31 +157,31 @@ func (d *PciDev) InitNickName() {
switch {
case d.devType == PCI_CAP_EXP_TYPE_ROOT_PORT:
name = "ROOT"
case d.devType == PCI_CAP_EXP_TYPE_UPSTREAM && d.vendor == 0x8086:
case d.devType == PCI_CAP_EXP_TYPE_UPSTREAM && d.Vendor == 0x8086:
name = "ISW"
case d.devType == PCI_CAP_EXP_TYPE_UPSTREAM && d.vendor == 0x10b5:
case d.devType == PCI_CAP_EXP_TYPE_UPSTREAM && d.Vendor == 0x10b5:
name = "PLX"
case d.devType == PCI_CAP_EXP_TYPE_UPSTREAM && d.vendor == 0x11f8:
case d.devType == PCI_CAP_EXP_TYPE_UPSTREAM && d.Vendor == 0x11f8:
name = "RIMFIRE"
case d.devType == PCI_CAP_EXP_TYPE_DOWNSTREAM:
name = fmt.Sprintf("p%d", d.parent.downPorts)
d.parent.downPorts++
separator = ""
case d.devType == PCI_CAP_EXP_TYPE_ENDPOINT && d.vendor == 0x15b7:
case d.devType == PCI_CAP_EXP_TYPE_ENDPOINT && d.Vendor == 0x15b7:
name = "sandisk"
case d.devType == PCI_CAP_EXP_TYPE_ENDPOINT && d.vendor == 0x15b3 && d.devFn == 0:
case d.devType == PCI_CAP_EXP_TYPE_ENDPOINT && d.Vendor == 0x15b3 && d.devFn == 0:
name = "MLX"
case d.devType == PCI_CAP_EXP_TYPE_PCI_BRIDGE && d.vendor == 0x1a03:
case d.devType == PCI_CAP_EXP_TYPE_PCI_BRIDGE && d.Vendor == 0x1a03:
name = "AST"
case d.devType == PCI_CAP_EXP_TYPE_ENDPOINT && d.vendor == 0x8086 && d.devClass == 0x0200:
case d.devType == PCI_CAP_EXP_TYPE_ENDPOINT && d.Vendor == 0x8086 && d.devClass == 0x0200:
name = "IETH"
case d.devType == PCI_CAP_EXP_TYPE_ENDPOINT && d.vendor == 0x1425 && d.devClass == 0x0200 && d.devFn == 0:
case d.devType == PCI_CAP_EXP_TYPE_ENDPOINT && d.Vendor == 0x1425 && d.devClass == 0x0200 && d.devFn == 0:
name = "CHL"
case d.devType == PCI_CAP_EXP_TYPE_ENDPOINT && d.vendor == 0x8086 && d.devClass == 0x0106:
case d.devType == PCI_CAP_EXP_TYPE_ENDPOINT && d.Vendor == 0x8086 && d.devClass == 0x0106:
name = "INTEL-SATA"
case d.devType == PCI_CAP_EXP_TYPE_ENDPOINT && d.vendor == 0x8086 && d.devClass == 0x0107:
case d.devType == PCI_CAP_EXP_TYPE_ENDPOINT && d.Vendor == 0x8086 && d.devClass == 0x0107:
name = "INTEL-SAS"
case d.devType == PCI_CAP_EXP_TYPE_ENDPOINT && d.vendor == 0x1000 && d.devClass == 0x0107:
case d.devType == PCI_CAP_EXP_TYPE_ENDPOINT && d.Vendor == 0x1000 && d.devClass == 0x0107:
name = "LSI-SAS"
}
if separator == "" {
Expand Down Expand Up @@ -213,7 +213,7 @@ func (d *PciDev) InitNickName() {

func (w *World) FindById(vid uint16, did uint16) (l []*PciDev) {
for _, d := range w.Devs {
if d.vendor == vid && d.device == did {
if d.Vendor == vid && d.Device == did {
l = append(l, d)
}
}
Expand All @@ -230,7 +230,8 @@ func PciInit() *World {
if upDev != nil {
parentName = upDev.Name
d.parent = upDev
if d.devFn == 0 && (upDev.devType == PCI_CAP_EXP_TYPE_ROOT_PORT || upDev.devType == PCI_CAP_EXP_TYPE_DOWNSTREAM) {
if d.devFn == 0 && (upDev.devType == PCI_CAP_EXP_TYPE_ROOT_PORT || upDev.devType == PCI_CAP_EXP_TYPE_DOWNSTREAM) &&
(d.devType == PCI_CAP_EXP_TYPE_ENDPOINT || d.devType == PCI_CAP_EXP_TYPE_UPSTREAM) {
upDev.LnkChild = d
}
}
Expand Down

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