update testbench, makefile, and script

src/main/java/de/tum/in/www1/artemis/config/icl/BuildAgentConfiguration.java

@@ -89,7 +89,7 @@ public HostConfig hostConfig() {
                 formatMemory(memorySwap), pidsLimit);
 
         return HostConfig.newHostConfig().withCpuQuota(cpuCount * cpuPeriod).withCpuPeriod(cpuPeriod).withMemory(memory).withMemorySwap(memorySwap).withPidsLimit(pidsLimit)
-                .withAutoRemove(true);
+                .withAutoRemove(false);
     }
 
     /**

src/main/resources/templates/aeolus/vhdl/default.sh

@@ -24,10 +24,12 @@ provide_environment_information () {
   fi
 }
 
-prepare_makefile () {
-  echo '⚙️ executing prepare_makefile'
+prepare_files () {
+  echo '⚙️ executing prepare_files'
   rm -f assignment/{GNUmakefile, Makefile, makefile}
+  rm -f assignment/*_tb.vhd
   cp -f tests/Makefile assignment/Makefile || exit 2
+  cp -f tests/*_tb.vhd assignment/ || exit 2
 }
 
 run_and_compile () {
@@ -61,7 +63,7 @@ main () {
   cd "${AEOLUS_INITIAL_DIRECTORY}"
   bash -c "source ${_script_name} aeolus_sourcing; provide_environment_information"
   cd "${AEOLUS_INITIAL_DIRECTORY}"
-  bash -c "source ${_script_name} aeolus_sourcing; prepare_makefile"
+  bash -c "source ${_script_name} aeolus_sourcing; prepare_files"
   cd "${AEOLUS_INITIAL_DIRECTORY}"
   bash -c "source ${_script_name} aeolus_sourcing; run_and_compile"
 }

src/main/resources/templates/aeolus/vhdl/default.yaml

@@ -22,10 +22,12 @@ actions:
           echo "$REQ_FILE does not exist"
       fi
     runAlways: false
-  - name: prepare_makefile
+  - name: prepare_files
     script: |-
       rm -f assignment/{GNUmakefile, Makefile, makefile}
+      rm -f assignment/*_tb.vhd
       cp -f tests/Makefile assignment/Makefile || exit 2
+      cp -f tests/*_tb.vhd assignment/ || exit 2
     runAlways: false
   - name: run_and_compile
     script: |-

src/main/resources/templates/vhdl/exercise/Makefile

@@ -3,6 +3,8 @@ NAME=verzoegerung
 all:
 	ghdl -a $(NAME).vhd
 	ghdl -a $(NAME)_tb.vhd
+	ghdl -e $(NAME)_tb
+	ghdl -r $(NAME)_tb
 
 clean:
 	rm *.o

src/main/resources/templates/vhdl/exercise/verzoegerung_tb.vhd

@@ -6,14 +6,14 @@ end verzoegerung_tb;
 
 architecture behavior of verzoegerung_tb is
 
-    component verzoegerung 
+    component verzoegerung
     port(
        CLK, START : in std_logic;
-        STOP : in std_logic;        -- Aufgabe 2
-        ALARM : out std_logic
-        );
+       STOP : in std_logic;        -- Aufgabe 2
+       ALARM : out std_logic
+    );
     end component;
-    
+
    signal START : std_logic := '0';
    signal STOP : std_logic := '0';
    signal CLK : std_logic := '0';
@@ -23,59 +23,115 @@ architecture behavior of verzoegerung_tb is
 
 begin
 
-   uut: verzoegerung port map (START => START, STOP => STOP, CLK => CLK,
-          			ALARM => ALARM
-        );
-
-  p0 :process
-  begin
-	  CLK <= '0';
-	  wait for clk_period/2;
-	  CLK <= '1';
-	  wait for clk_period/2;
-  end process;
-
-  p1: process
-  begin  
-
-          wait for 2 * clk_period;
-	  START <= '1';
-	  wait for clk_period;
-
-          wait for clk_period;
-
-          wait for clk_period;
-
-          wait for clk_period;
-
-          wait for clk_period;
-
-          wait for clk_period;
-
-
-	  START <= '0';
-
-          wait for clk_period;
-
-          START <= '1';
-
-          wait for clk_period;
-
-          wait for clk_period;
-
-          STOP <= '1';
-
-          wait for clk_period;
-
-          wait for clk_period;
-
-          wait for clk_period;
-
-          wait for clk_period;
-
-
-
-  end process;
-
-
-end;
+   uut: verzoegerung port map (
+       START => START,
+       STOP => STOP,
+       CLK => CLK,
+       ALARM => ALARM
+   );
+
+   -- Clock generation process
+   p0 : process
+   begin
+       CLK <= '0';
+       wait for clk_period / 2;
+       CLK <= '1';
+       wait for clk_period / 2;
+   end process;
+
+   -- Stimulus process
+   p1: process
+   begin
+       wait for 2 * clk_period;
+       START <= '1';
+
+       -- Assertions after START signal is set to '1'
+       wait for clk_period;
+       if (ALARM = '1') then
+           report "ALARM should be '0' after 1 clock cycle" severity error;
+       else
+           report "ALARM is '0' after 1 clock cycle" severity note;
+       end if;
+
+       wait for clk_period;
+       if (ALARM = '1') then
+           report "ALARM should be '0' after 2 clock cycles" severity error;
+       else
+           report "ALARM is '0' after 2 clock cycles" severity note;
+       end if;
+
+       wait for clk_period;
+       if (ALARM = '1') then
+           report "ALARM should be '0' after 3 clock cycles" severity error;
+       else
+           report "ALARM is '0' after 3 clock cycles" severity note;
+       end if;
+
+       wait for clk_period;
+       if (ALARM = '0') then
+           report "ALARM should be '1' after 4 clock cycles" severity error;
+       else
+           report "ALARM is '1' after 4 clock cycles" severity note;
+       end if;
+
+       START <= '0';
+       wait for clk_period;
+       if (ALARM = '1') then
+           report "ALARM should be '1' after START is deasserted" severity error;
+       else
+           report "ALARM is '0' after START is deasserted" severity note;
+       end if;
+
+       -- Test Case 2: Apply START again to check reset of alarm
+       wait for clk_period;
+       START <= '1';
+
+       wait for clk_period;
+       if (ALARM = '1') then
+           report "ALARM should be '0' after 1 clock cycle" severity error;
+       else
+           report "ALARM is '0' after 1 clock cycle" severity note;
+       end if;
+
+       wait for clk_period;
+       if (ALARM = '1') then
+           report "ALARM should be '0' after 2 clock cycles" severity error;
+       else
+           report "ALARM is '0' after 2 clock cycles" severity note;
+       end if;
+
+       wait for clk_period;
+       if (ALARM = '1') then
+           report "ALARM should be '0' after 3 clock cycles" severity error;
+       else
+           report "ALARM is '0' after 3 clock cycles" severity note;
+       end if;
+
+       wait for clk_period;
+       if (ALARM = '0') then
+           report "ALARM should be '1' after 4 clock cycles" severity error;
+       else
+           report "ALARM is '1' after 4 clock cycles" severity note;
+       end if;
+
+       wait for clk_period;
+       STOP <= '1';
+
+       -- Assertions for STOP signal
+       wait for clk_period;
+       if (ALARM = '1') then
+           report "ALARM should be '0' after 1 clock cycle" severity error;
+       else
+           report "ALARM is '0' after 1 clock cycle" severity note;
+       end if;
+
+       -- Wait for a few clock cycles to observe the behavior after STOP is deasserted
+       wait for 4 * clk_period;
+       STOP <= '0';
+       START <= '0';
+
+       -- Finish simulation
+       wait;
+   end process;
+
+end behavior;

src/main/resources/templates/vhdl/solution/Makefile

@@ -3,6 +3,8 @@ NAME=verzoegerung
 all:
 	ghdl -a $(NAME).vhd
 	ghdl -a $(NAME)_tb.vhd
+	ghdl -e $(NAME)_tb
+	ghdl -r $(NAME)_tb
 
 clean:
 	rm *.o

src/main/resources/templates/vhdl/solution/verzoegerung.vhd

@@ -5,7 +5,7 @@ use ieee.numeric_std.all;
 entity verzoegerung is
 port(
         CLK, START : in std_logic;
-        STOP : in std_logic;        -- Aufgabe 2 
+        STOP : in std_logic;        -- Aufgabe 2
         ALARM : out std_logic
     );
 end entity;
@@ -20,26 +20,26 @@ process(CLK)
 begin
 
     if rising_edge(CLK) then
-    
---        if STOP = '1' then      -- synchroner Reset (Aufgabe 2), für Afgabe 2 unkommentieren
---            z <= "000";
-        
+
+        if STOP = '1' then      -- synchroner Reset (Aufgabe 2), für Afgabe 2 unkommentieren
+            z <= "000";
+
         else
             case z is
                 when "000" =>       -- Startzustand
-                                if START = '1' then 
+                                if START = '1' then
                                     z <= "001";
                                 end if;
-                when "001" | "010" | "011" =>   -- Wartezustaende    
-                                    z <= z + 1; 
+                when "001" | "010" | "011" =>   -- Wartezustaende
+                                    z <= z + 1;
                 when "100" =>       -- Alarmzustand
                                 if START = '0' then
                                     z <= "000";
                                 end if;
-                when others => 
-            
-            end case;   
---        end if;               -- für Aufgabe 2 unkommentieren 
+                when others =>
+
+            end case;
+        end if;               -- für Aufgabe 2 unkommentieren
     end if;
 
 end process;