native codegen tells me Warning: Native code generation is not supported in current configuration

[walksanatora]

is there a way to get it to be supported?
I am running on x86_64 linux (Arch) using the AUR package. is there some flag or something I have to pass to enable native codegen

[zeux]

We don't maintain AUR packages but it doesn't look like their build instructions are special in any way. What's your hardware / can you paste the output of /proc/cpuinfo for one of the cores?

[walksanatora]

processor	: 0
vendor_id	: GenuineIntel
cpu family	: 6
model		: 156
model name	: Intel(R) Pentium(R) Silver N6000 @ 1.10GHz
stepping	: 0
microcode	: 0x24000024
cpu MHz		: 2399.991
cache size	: 4096 KB
physical id	: 0
siblings	: 4
core id		: 0
cpu cores	: 4
apicid		: 0
initial apicid	: 0
fpu		: yes
fpu_exception	: yes
cpuid level	: 27
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 sdbg cx16 xtpr pdcm sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave rdrand lahf_lm 3dnowprefetch cpuid_fault epb cat_l2 cdp_l2 ssbd ibrs ibpb stibp ibrs_enhanced tpr_shadow flexpriority ept vpid ept_ad fsgsbase tsc_adjust smep erms rdt_a rdseed smap clflushopt clwb intel_pt sha_ni xsaveopt xsavec xgetbv1 xsaves split_lock_detect dtherm ida arat pln pts hwp hwp_notify hwp_act_window hwp_epp hwp_pkg_req vnmi umip waitpkg gfni rdpid movdiri movdir64b md_clear flush_l1d arch_capabilities
vmx flags	: vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest vapic_reg vid ple shadow_vmcs ept_mode_based_exec tsc_scaling usr_wait_pause
bugs		: spectre_v1 spectre_v2 spec_store_bypass swapgs srbds mmio_stale_data
bogomips	: 2228.00
clflush size	: 64
cache_alignment	: 64
address sizes	: 39 bits physical, 48 bits virtual
power management:

[zeux]

Please refer to the recent post that outlines the requirements. Your CPU doesn't support AVX1 and we are not planning to support systems without this instruction set.

[walksanatora]

is there no way to enable/get AVX1