Set exception and interrupt delegation for S-mode

lupyuen · Jan 19, 2024 · 9536e86 · 9536e86
1 parent 48e7121
commit 9536e86
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Showing 2 changed files with 12 additions and 3 deletions.
diff --git a/riscv_cpu.c b/riscv_cpu.c
@@ -1096,9 +1096,8 @@ static void raise_exception2(RISCVCPUState *s, uint32_t cause,
         flag = 1;
         flag = (cause & CAUSE_INTERRUPT) == 0;
         //// Previously: if (cause == CAUSE_SUPERVISOR_ECALL || cause == CAUSE_ILLEGAL_INSTRUCTION)
-        if (cause == CAUSE_SUPERVISOR_ECALL) ////
-            //// Previously: flag = 0;
-            flag = 1; ////
+        if (cause == CAUSE_SUPERVISOR_ECALL || cause == CAUSE_USER_ECALL) ////
+            flag = 0;
 #endif
         if (flag) {
             log_printf("raise_exception: cause=0x%08x tval=0x", cause);

diff --git a/riscv_machine.c b/riscv_machine.c
@@ -873,6 +873,16 @@ static void copy_bios(RISCVMachine *s, const uint8_t *buf, int buf_len,
 
     //// Begin Test: Start in Supervisor Mode
     uint32_t pc = 4;
+
+    // Set exception and interrupt delegation for S-mode
+    // WRITE_CSR(medeleg, 0xffff);
+    q[pc++] = 0x000167c1;  // lui a5, 0x10 ; nop
+    q[pc++] = 0x000137fd;  // addiw a5, a5, -1 ; nop
+    q[pc++] = 0x30279073;  // csrw medeleg, a5
+
+    // WRITE_CSR(mideleg, 0xffff);
+    q[pc++] = 0x30379073;  // csrw mideleg, a5
+
     // Set mstatus to S-mode and enable SUM
     // CLEAR_CSR(mstatus, ~MSTATUS_MPP_MASK);
     q[pc++] = 0x000177f9;  // lui a5, 0xffffe ; nop