TODO: Support for RISC-V Star64 JH7110 SBC (Branch star64d)

.gitignore

@@ -60,3 +60,5 @@ uImage
 .vscode
 .DS_Store
 tools/gdb/__pycache__
+initrd
+init.S

arch/risc-v/include/qemu-rv/irq.h

@@ -31,8 +31,12 @@
 
 /* Map RISC-V exception code to NuttX IRQ */
 
-#define QEMU_RV_IRQ_UART0  (RISCV_IRQ_MEXT + 10)
+//// "JH7110 Interrupt Connections" says that Global Interrupts are 0 to 126 (127 total interrupts)
+//// https://doc-en.rvspace.org/JH7110/TRM/JH7110_TRM/interrupt_connections.html
+#define NR_IRQS (RISCV_IRQ_SEXT + 127)
 
-#define NR_IRQS (QEMU_RV_IRQ_UART0 + 1)
+////#define QEMU_RV_IRQ_UART0  (RISCV_IRQ_MEXT + 10)
+
+////#define NR_IRQS (QEMU_RV_IRQ_UART0 + 1)
 
 #endif /* __ARCH_RISCV_INCLUDE_QEMU_RV_IRQ_H */

arch/risc-v/src/common/riscv_hostfs.c

@@ -31,6 +31,8 @@
 #include <string.h>
 #include <syscall.h>
 #include <unistd.h>
+#include <debug.h>////
+#include <assert.h>////
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -52,6 +54,9 @@
 
 static long host_call(unsigned int nbr, void *parm, size_t size)
 {
+  _info("nbr=0x%x, parm=%p, size=%ld\n", nbr, parm, size);////
+  DEBUGPANIC();//// Semihosting not supported
+
 #ifdef CONFIG_RISCV_SEMIHOSTING_HOSTFS_CACHE_COHERENCE
   up_clean_dcache(parm, parm + size);
 #endif

arch/risc-v/src/qemu-rv/hardware/qemu_rv_memorymap.h

@@ -28,7 +28,7 @@
 /* Register Base Address ****************************************************/
 
 #define QEMU_RV_CLINT_BASE   0x02000000
-#define QEMU_RV_ACLINT_BASE  0x02f00000
+////#define QEMU_RV_ACLINT_BASE  0x02f00000
 #define QEMU_RV_PLIC_BASE    0x0c000000
 
 #endif /* __ARCH_RISCV_SRC_QEMU_RV_HARDWARE_QEMU_RV_MEMORYMAP_H */

arch/risc-v/src/qemu-rv/hardware/qemu_rv_plic.h

@@ -31,14 +31,32 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
+// | 0x0C00_0004 | 4B | RW | Source 1 priority
 #define QEMU_RV_PLIC_PRIORITY    (QEMU_RV_PLIC_BASE + 0x000000)
+
+// | 0x0C00_1000 | 4B | RO | Start of pending array
 #define QEMU_RV_PLIC_PENDING1    (QEMU_RV_PLIC_BASE + 0x001000)
 
+// Previously:
+// #define QEMU_RV_PLIC_PRIORITY    (QEMU_RV_PLIC_BASE + 0x000000)
+// #define QEMU_RV_PLIC_PENDING1    (QEMU_RV_PLIC_BASE + 0x001000)
+
 #ifdef CONFIG_ARCH_USE_S_MODE
-#  define QEMU_RV_PLIC_ENABLE1   (QEMU_RV_PLIC_BASE + 0x002080)
-#  define QEMU_RV_PLIC_ENABLE2   (QEMU_RV_PLIC_BASE + 0x002084)
-#  define QEMU_RV_PLIC_THRESHOLD (QEMU_RV_PLIC_BASE + 0x201000)
-#  define QEMU_RV_PLIC_CLAIM     (QEMU_RV_PLIC_BASE + 0x201004)
+// | 0x0C00_2100 | 4B | RW | Start Hart 1 S-Mode interrupt enables
+#  define QEMU_RV_PLIC_ENABLE1   (QEMU_RV_PLIC_BASE + 0x002100)
+#  define QEMU_RV_PLIC_ENABLE2   (QEMU_RV_PLIC_BASE + 0x002104)
+
+// | 0x0C20_2000 | 4B | RW | Hart 1 S-Mode priority threshold
+#  define QEMU_RV_PLIC_THRESHOLD (QEMU_RV_PLIC_BASE + 0x202000)
+
+// | 0x0C20_2004 | 4B | RW | Hart 1 S-Mode claim/complete 
+#  define QEMU_RV_PLIC_CLAIM     (QEMU_RV_PLIC_BASE + 0x202004)
+
+// Previously:
+// #  define QEMU_RV_PLIC_ENABLE1   (QEMU_RV_PLIC_BASE + 0x002080)
+// #  define QEMU_RV_PLIC_ENABLE2   (QEMU_RV_PLIC_BASE + 0x002084)
+// #  define QEMU_RV_PLIC_THRESHOLD (QEMU_RV_PLIC_BASE + 0x201000)
+// #  define QEMU_RV_PLIC_CLAIM     (QEMU_RV_PLIC_BASE + 0x201004)
 #else
 #  define QEMU_RV_PLIC_ENABLE1   (QEMU_RV_PLIC_BASE + 0x002000)
 #  define QEMU_RV_PLIC_ENABLE2   (QEMU_RV_PLIC_BASE + 0x002004)

arch/risc-v/src/qemu-rv/qemu_rv_head.S

@@ -40,17 +40,78 @@
   .global __start
 
 __start:
+  /* Begin Test */
+
+  /* DO NOT MODIFY. Image Header expected by Linux bootloaders.
+   *
+   * This `li` instruction has no meaningful effect except that
+   * its opcode forms the magic "MZ" signature of a PE/COFF file
+   * that is required for UEFI applications.
+   *
+   * Some bootloaders check the magic "MZ" to see if the image is a valid
+   * Linux image. But modifying the bootLoader is unnecessary unless we
+   * need to do a customized secure boot. So we just put "MZ" in the
+   * header to make the bootloader happy.
+   */
+
+  c.li    s4, -13              /* Magic Signature "MZ" (2 bytes) */
+  j       real_start           /* Jump to Kernel Start (2 bytes) */
+  .long   0                    /* Executable Code padded to 8 bytes */
+  .quad   0x200000             /* Image load offset from start of RAM */
+  /* TODO: _e_initstack - __start */
+  .quad   171644               /* Effective size of kernel image, little-endian */
+  .quad   0x0                  /* Kernel flags, little-endian */
+  .long   0x2                  /* Version of this header */
+  .long   0                    /* Reserved */
+  .quad   0                    /* Reserved */
+  .ascii  "RISCV\x00\x00\x00"  /* Magic number, "RISCV" (8 bytes) */
+  .ascii  "RSC\x05"            /* Magic number 2, "RSC\x05" (4 bytes) */
+  .long   0                    /* Reserved for PE COFF offset */
+
+real_start:
+
+  /* Load UART Base Address to Register t0 */
+  li  t0, 0x10000000
+
+  /* Load `1` to Register t1 */
+  li  t1, 0x31
+  /* Store byte from Register t1 to UART Base Address, Offset 0 */
+  sb  t1, 0(t0)
+
+  /* Load `2` to Register t1 */
+  li  t1, 0x32
+  /* Store byte from Register t1 to UART Base Address, Offset 0 */
+  sb  t1, 0(t0)
+
+  /* Load `3` to Register t1 */
+  li  t1, 0x33
+  /* Store byte from Register t1 to UART Base Address, Offset 0 */
+  sb  t1, 0(t0)
+
+  /* End Test */
 
   /* Load mhartid (cpuid) */
+  /* Previously: csrr a0, mhartid */
+
+  /* We assume that OpenSBI has passed Hart ID (value 1) in Register a0. */
+  /* But NuttX expects Hart ID to start at 0, so we subtract 1. */
+  addi a0, a0, -1
 
-  csrr a0, mhartid
+  /* Print the Hart ID */
+  addi t1, a0, 0x30
+  /* Store byte from Register t1 to UART Base Address, Offset 0 */
+  sb   t1, 0(t0)
 
   /* Set stack pointer to the idle thread stack */
 
   bnez a0, 1f
   la   sp, QEMU_RV_IDLESTACK_TOP
   j    2f
 1:
+  /* Print `4` */
+  li  t0, 0x10000000
+  li  t1, 0x34
+  sb  t1, 0(t0)
 
   /* Load the number of CPUs that the kernel supports */
 
@@ -63,10 +124,16 @@ __start:
   /* If a0 (mhartid) >= t1 (the number of CPUs), stop here */
 
   blt  a0, t1, 3f
-  csrw mie, zero
+  csrw sie, zero
+  /* Previously: csrw mie, zero */
   wfi
 
 3:
+  /* Print `5` */
+  li  t0, 0x10000000
+  li  t1, 0x35
+  sb  t1, 0(t0)
+
   /* To get g_cpu_basestack[mhartid], must get g_cpu_basestack first */
 
   la   t0, g_cpu_basestack
@@ -95,13 +162,24 @@ __start:
   add  sp, sp, t0
 
 2:
+  /* Print `6` */
+  li  t0, 0x10000000
+  li  t1, 0x36
+  sb  t1, 0(t0)
 
   /* Disable all interrupts (i.e. timer, external) in mie */
 
-	csrw	mie, zero
+  csrw	sie, zero
+  /* Previously: csrw	mie, zero */
 
   la   t0, __trap_vec
-  csrw mtvec, t0
+  csrw stvec, t0
+  /* Previously: csrw mtvec, t0 */
+
+  /* Print `7` */
+  li  t0, 0x10000000
+  li  t1, 0x37
+  sb  t1, 0(t0)
 
   /* Jump to qemu_rv_start */
 

arch/risc-v/src/qemu-rv/qemu_rv_irq.c

@@ -54,6 +54,15 @@ void up_irqinitialize(void)
   putreg32(0x0, QEMU_RV_PLIC_ENABLE1);
   putreg32(0x0, QEMU_RV_PLIC_ENABLE2);
 
+#ifdef NOTUSED
+  // Disable All Global Interrupts for Hart 1 Machine-Mode
+  // | 0x0C00_2080 | 4B | RW | Start Hart 1 M-Mode interrupt enables
+  #define QEMU_RV_PLIC_ENABLE1_MMODE   (QEMU_RV_PLIC_BASE + 0x002080)
+  #define QEMU_RV_PLIC_ENABLE2_MMODE   (QEMU_RV_PLIC_BASE + 0x002084)
+  putreg32(0x0, QEMU_RV_PLIC_ENABLE1_MMODE);
+  putreg32(0x0, QEMU_RV_PLIC_ENABLE2_MMODE);
+#endif  // NOTUSED
+
   /* Colorize the interrupt stack for debug purposes */
 
 #if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 15
@@ -65,7 +74,8 @@ void up_irqinitialize(void)
 
   int id;
 
-  for (id = 1; id <= 52; id++)
+  ////TODO: Why 52 PLIC Interrupts?
+  for (id = 1; id <= NR_IRQS; id++) //// Changed 52 to NR_IRQS
     {
       putreg32(1, (uintptr_t)(QEMU_RV_PLIC_PRIORITY + 4 * id));
     }
@@ -104,6 +114,7 @@ void up_irqinitialize(void)
 
 void up_disable_irq(int irq)
 {
+  _info("irq=%d\n", irq);////
   int extirq;
 
   if (irq == RISCV_IRQ_SOFT)
@@ -124,7 +135,7 @@ void up_disable_irq(int irq)
 
       /* Clear enable bit for the irq */
 
-      if (0 <= extirq && extirq <= 63)
+      if (0 <= extirq && extirq <= 63) ////TODO: Why 63?
         {
           modifyreg32(QEMU_RV_PLIC_ENABLE1 + (4 * (extirq / 32)),
                       1 << (extirq % 32), 0);
@@ -146,23 +157,27 @@ void up_disable_irq(int irq)
 
 void up_enable_irq(int irq)
 {
+  _info("irq=%d\n", irq);////
   int extirq;
 
   if (irq == RISCV_IRQ_SOFT)
     {
+      _info("RISCV_IRQ_SOFT=%d\n", RISCV_IRQ_SOFT);////
       /* Read m/sstatus & set machine software interrupt enable in m/sie */
 
       SET_CSR(CSR_IE, IE_SIE);
     }
   else if (irq == RISCV_IRQ_TIMER)
     {
+      _info("RISCV_IRQ_TIMER=%d\n", RISCV_IRQ_TIMER);////
       /* Read m/sstatus & set timer interrupt enable in m/sie */
 
       SET_CSR(CSR_IE, IE_TIE);
     }
 #ifdef CONFIG_BUILD_KERNEL
   else if (irq == RISCV_IRQ_MTIMER)
     {
+      _info("RISCV_IRQ_MTIMER=%d\n", RISCV_IRQ_MTIMER);////
       /* Read m/sstatus & set timer interrupt enable in m/sie */
 
       SET_CSR(mie, MIE_MTIE);
@@ -171,10 +186,11 @@ void up_enable_irq(int irq)
   else if (irq > RISCV_IRQ_EXT)
     {
       extirq = irq - RISCV_IRQ_EXT;
+      _info("extirq=%d, RISCV_IRQ_EXT=%d\n", extirq, RISCV_IRQ_EXT);////
 
       /* Set enable bit for the irq */
 
-      if (0 <= extirq && extirq <= 63)
+      if (0 <= extirq && extirq <= 63) ////TODO: Why 63?
         {
           modifyreg32(QEMU_RV_PLIC_ENABLE1 + (4 * (extirq / 32)),
                       0, 1 << (extirq % 32));
@@ -184,10 +200,12 @@ void up_enable_irq(int irq)
           PANIC();
         }
     }
+  else { _info("***NOT ENABLED: irq=%d\n", irq); }////
 }
 
 irqstate_t up_irq_enable(void)
 {
+  _info("\n");////
   irqstate_t oldstat;
 
   /* Enable external interrupts (mie/sie) */

arch/risc-v/src/qemu-rv/qemu_rv_irq_dispatch.c

@@ -26,6 +26,7 @@
 
 #include <stdint.h>
 #include <assert.h>
+#include <debug.h>///
 
 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
@@ -79,6 +80,8 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
 
   if (RISCV_IRQ_EXT <= irq)
     {
+      ////_info("irq=%d, RISCV_IRQ_EXT=%d\n", irq, RISCV_IRQ_EXT);////
+      ////up_putc('.'); up_mdelay(1000);////
       /* Then write PLIC_CLAIM to clear pending in PLIC */
 
       putreg32(irq - RISCV_IRQ_EXT, QEMU_RV_PLIC_CLAIM);

arch/risc-v/src/qemu-rv/qemu_rv_mm_init.c

@@ -43,7 +43,7 @@
 /* Map the whole I/O memory with vaddr = paddr mappings */
 
 #define MMU_IO_BASE     (0x00000000)
-#define MMU_IO_SIZE     (0x80000000)
+#define MMU_IO_SIZE     (0x40000000)
 
 #ifdef CONFIG_ARCH_MMU_TYPE_SV32
 
@@ -269,6 +269,22 @@ void qemu_rv_kernel_mappings(void)
   binfo("map kernel data\n");
   map_region(KSRAM_START, KSRAM_START, KSRAM_SIZE, MMU_KDATA_FLAGS);
 
+  // Added RAM Disk
+  //// From nuttx/boards/risc-v/litex/arty_a7/include/board_memorymap.h
+  /* ramdisk (RW) */
+  extern uint8_t          __ramdisk_start[];
+  extern uint8_t          __ramdisk_size[];
+  // Copy 0x46100000 to __ramdisk_start (__ramdisk_size bytes)
+  // TODO: RAM Disk must not exceed __ramdisk_size bytes
+  memcpy((void *)__ramdisk_start, (void *)0x46100000, (size_t)__ramdisk_size);
+
+#ifdef NOTUSED
+  /* Added RAM Disk */
+  _info("map RAM Disk\n");
+  map_region((uintptr_t)__ramdisk_start, (uintptr_t)__ramdisk_start, (uintptr_t)__ramdisk_size, MMU_KDATA_FLAGS);
+  _info("map RAM Disk done\n");
+#endif  // NOTUSED
+
 #ifdef CONFIG_ARCH_MMU_TYPE_SV39
 
   /* Connect the L1 and L2 page tables for the kernel text and data */