tinyemu2: Full Version of Apache NuttX RTOS for TinyEMU

arch/risc-v/src/qemu-rv/hardware/qemu_rv_memorymap.h

@@ -27,8 +27,8 @@
 
 /* Register Base Address ****************************************************/
 
-#define QEMU_RV_CLINT_BASE   0x02000000
-#define QEMU_RV_ACLINT_BASE  0x02f00000
-#define QEMU_RV_PLIC_BASE    0x0c000000
+#define QEMU_RV_CLINT_BASE   0x02000000  //// CLINT_BASE_ADDR. Previously: 0x02000000
+////#define QEMU_RV_ACLINT_BASE  0x02f00000
+#define QEMU_RV_PLIC_BASE    0x40100000  //// PLIC_BASE_ADDR. Previously: 0x0c000000
 
 #endif /* __ARCH_RISCV_SRC_QEMU_RV_HARDWARE_QEMU_RV_MEMORYMAP_H */

arch/risc-v/src/qemu-rv/qemu_rv_head.S

@@ -41,6 +41,25 @@
 
 __start:
 
+  /* Print `123` to HTIF Console */
+  /* Load HTIF Base Address to Register t0 */
+  li  t0, 0x40008000
+
+  /* Load to Register t1 the HTIF Command to print `1` */
+  li  t1, 0x0101000000000031
+  /* Store 64-bit double-word from Register t1 to HTIF Base Address, Offset 0 */
+  sd  t1, 0(t0)
+
+  /* Load to Register t1 the HTIF Command to print `2` */
+  li  t1, 0x0101000000000032
+  /* Store 64-bit double-word from Register t1 to HTIF Base Address, Offset 0 */
+  sd  t1, 0(t0)
+
+  /* Load to Register t1 the HTIF Command to print `3` */
+  li  t1, 0x0101000000000033
+  /* Store 64-bit double-word from Register t1 to HTIF Base Address, Offset 0 */
+  sd  t1, 0(t0)
+
   /* Preserve a1 as it contains the pointer to DTB */
   /* Load mhartid (cpuid) */
 

arch/risc-v/src/qemu-rv/qemu_rv_irq.c

@@ -192,7 +192,21 @@ irqstate_t up_irq_enable(void)
 
   /* Enable external interrupts (mie/sie) */
 
+  uint64_t mie0 = READ_CSR(mie); if (mie0 == 0) { _info("Before mie: %p\n", mie0); }////
   SET_CSR(CSR_IE, IE_EIE);
+  uint64_t mie1 = READ_CSR(mie); if (mie0 == 0) { _info("After mie: %p\n", mie1); }////
+
+  // TODO: TinyEMU supports SEIE but not MEIE!
+  uint64_t mie = READ_CSR(mie); if (mie0 == 0) { _info("mie: %p\n", mie); }////
+
+  // TODO: This doesn't work
+  // Enable MEIE: Machine-Mode External Interrupt  
+  // WRITE_CSR(mie, mie | (1 << 11));
+
+  // TODO: This works, but we need MEIE, not SEIE. We patch this in riscv_dispatch_irq()
+  // Enable SEIE: Supervisor-Mode External Interrupt
+  WRITE_CSR(mie, mie | (1 << 9));
+  mie = READ_CSR(mie); if (mie0 == 0) { _info("mie: %p\n", mie); }////
 
   /* Read and enable global interrupts (M/SIE) in m/sstatus */
 

arch/risc-v/src/qemu-rv/qemu_rv_irq_dispatch.c

@@ -56,6 +56,7 @@
 void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
 {
   int irq = (vector >> RV_IRQ_MASK) | (vector & 0xf);
+  if (irq == RISCV_IRQ_SEXT) { irq = RISCV_IRQ_MEXT; } ////TODO: TinyEMU works only with SEIE, not MEIE
 
   /* Firstly, check if the irq is machine external interrupt */
 

arch/risc-v/src/qemu-rv/qemu_rv_start.c

@@ -26,7 +26,6 @@
 
 #include <nuttx/init.h>
 #include <nuttx/arch.h>
-#include <nuttx/serial/uart_16550.h>
 #include <arch/board/board.h>
 
 #include "riscv_internal.h"
@@ -230,10 +229,43 @@ void qemu_rv_start(int mhartid, const char *dtb)
 
 void riscv_earlyserialinit(void)
 {
-  u16550_earlyserialinit();
 }
 
 void riscv_serialinit(void)
 {
-  u16550_serialinit();
+  // Init the VirtIO Devices
+  void qemu_virtio_register_mmio_devices(void);
+  qemu_virtio_register_mmio_devices();
+}
+
+// Print to HTIF Console
+static void htif_putc(int ch)
+{
+  // Hardcode the HTIF Base Address and print: device=1, cmd=1, buf=ch
+  *(volatile uint64_t *) 0x40008000 = 0x0101000000000000ul | ch;
+}
+
+int up_putc(int ch)
+{
+  irqstate_t flags;
+
+  /* All interrupts must be disabled to prevent re-entrancy and to prevent
+   * interrupts from firing in the serial driver code.
+   */
+
+  flags = enter_critical_section();
+
+  /* Check for LF */
+
+  if (ch == '\n')
+    {
+      /* Add CR */
+
+      htif_putc('\r');
+    }
+
+  htif_putc(ch);
+  leave_critical_section(flags);
+
+  return ch;
 }

boards/risc-v/qemu-rv/rv-virt/configs/nsh64/defconfig

@@ -7,13 +7,6 @@
 #
 # CONFIG_DISABLE_OS_API is not set
 # CONFIG_NSH_DISABLE_LOSMART is not set
-CONFIG_16550_ADDRWIDTH=0
-CONFIG_16550_UART0=y
-CONFIG_16550_UART0_BASE=0x10000000
-CONFIG_16550_UART0_CLOCK=3686400
-CONFIG_16550_UART0_IRQ=37
-CONFIG_16550_UART0_SERIAL_CONSOLE=y
-CONFIG_16550_UART=y
 CONFIG_ARCH="risc-v"
 CONFIG_ARCH_BOARD="rv-virt"
 CONFIG_ARCH_BOARD_QEMU_RV_VIRT=y
@@ -29,12 +22,40 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BCH=y
 CONFIG_BOARD_LOOPSPERMSEC=6366
 CONFIG_BUILTIN=y
+CONFIG_DEBUG_ASSERTIONS=y
+CONFIG_DEBUG_ASSERTIONS_EXPRESSION=y
+CONFIG_DEBUG_BINFMT=y
+CONFIG_DEBUG_BINFMT_ERROR=y
+CONFIG_DEBUG_BINFMT_WARN=y
+CONFIG_DEBUG_FEATURES=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_FS_ERROR=y
+CONFIG_DEBUG_FS_WARN=y
 CONFIG_DEBUG_FULLOPT=y
+CONFIG_DEBUG_IPC=y
+CONFIG_DEBUG_IPC_ERROR=y
+CONFIG_DEBUG_IPC_WARN=y
+CONFIG_DEBUG_LIB=y
+CONFIG_DEBUG_LIB_ERROR=y
+CONFIG_DEBUG_LIB_WARN=y
+CONFIG_DEBUG_SCHED=y
+CONFIG_DEBUG_SCHED_ERROR=y
+CONFIG_DEBUG_SCHED_WARN=y
 CONFIG_DEBUG_SYMBOLS=y
+CONFIG_DEBUG_TIMER=y
+CONFIG_DEBUG_TIMER_ERROR=y
+CONFIG_DEBUG_TIMER_WARN=y
+CONFIG_DEBUG_VIRTIO=y
+CONFIG_DEBUG_VIRTIO_ERROR=y
+CONFIG_DEBUG_VIRTIO_WARN=y
 CONFIG_DEVICE_TREE=y
+CONFIG_DEV_SIMPLE_ADDRENV=y
 CONFIG_DEV_ZERO=y
+CONFIG_DRIVERS_VIRTIO=y
+CONFIG_DRIVERS_VIRTIO_MMIO=y
+CONFIG_DRIVERS_VIRTIO_SERIAL=y
 CONFIG_ELF=y
-CONFIG_EXAMPLES_HELLO=m
+CONFIG_EXAMPLES_HELLO=y
 CONFIG_FS_HOSTFS=y
 CONFIG_FS_PROCFS=y
 CONFIG_IDLETHREAD_STACKSIZE=2048
@@ -45,6 +66,7 @@ CONFIG_LIBC_ENVPATH=y
 CONFIG_LIBC_EXECFUNCS=y
 CONFIG_LIBC_PERROR_STDOUT=y
 CONFIG_LIBC_STRERROR=y
+CONFIG_NDEBUG=y
 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6
 CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
@@ -60,7 +82,6 @@ CONFIG_READLINE_CMD_HISTORY=y
 CONFIG_RISCV_SEMIHOSTING_HOSTFS=y
 CONFIG_RR_INTERVAL=200
 CONFIG_SCHED_WAITPID=y
-CONFIG_SERIAL_UART_ARCH_MMIO=y
 CONFIG_STACK_COLORATION=y
 CONFIG_START_MONTH=12
 CONFIG_START_YEAR=2021

boards/risc-v/qemu-rv/rv-virt/src/qemu_rv_appinit.c

@@ -38,14 +38,10 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-#define QEMU_VIRTIO_MMIO_BASE    0x10001000
-#define QEMU_VIRTIO_MMIO_REGSIZE 0x1000
-#ifdef CONFIG_ARCH_USE_S_MODE
-#  define QEMU_VIRTIO_MMIO_IRQ   26
-#else
-#  define QEMU_VIRTIO_MMIO_IRQ   28
-#endif
-#define QEMU_VIRTIO_MMIO_NUM     8
+#define QEMU_VIRTIO_MMIO_BASE    0x40010000 // VIRTIO_BASE_ADDR. Previously: 0x10001000
+#define QEMU_VIRTIO_MMIO_REGSIZE 0x1000     // VIRTIO_SIZE
+#define QEMU_VIRTIO_MMIO_IRQ     (RISCV_IRQ_EXT + 1) // VIRTIO_IRQ
+#define QEMU_VIRTIO_MMIO_NUM     1  // Number of VirtIO Devices. Previously: 8
 
 /****************************************************************************
  * Private Functions
@@ -56,7 +52,8 @@
  ****************************************************************************/
 
 #ifdef CONFIG_DRIVERS_VIRTIO_MMIO
-static void qemu_virtio_register_mmio_devices(void)
+////Previously: static. Now called by nuttx/arch/risc-v/src/qemu-rv/qemu_rv_start.c
+void qemu_virtio_register_mmio_devices(void)
 {
   uintptr_t virtio = (uintptr_t)QEMU_VIRTIO_MMIO_BASE;
   size_t size = QEMU_VIRTIO_MMIO_REGSIZE;
@@ -113,7 +110,8 @@ int board_app_initialize(uintptr_t arg)
 #endif
 
 #ifdef CONFIG_DRIVERS_VIRTIO_MMIO
-  qemu_virtio_register_mmio_devices();
+  //// Moved to nuttx/arch/risc-v/src/qemu-rv/qemu_rv_start.c
+  //// Previously: qemu_virtio_register_mmio_devices();
 #endif
 
   return OK;

drivers/virtio/virtio-serial.c

@@ -480,6 +480,9 @@ static int virtio_serial_init(FAR struct virtio_serial_priv_s *priv,
       goto err_with_recv;
     }
 
+  //// TinyEMU needs NuttX to echo the keypress and change CR to NL
+  udev->isconsole = true; ////
+
   /* Initialize the virtio device */
 
   virtio_set_status(vdev, VIRTIO_CONFIG_STATUS_DRIVER);
@@ -550,7 +553,7 @@ static int virtio_serial_probe(FAR struct virtio_device *vdev)
 
   /* Uart driver register */
 
-  snprintf(priv->name, NAME_MAX, "/dev/ttyV%d", g_virtio_serial_idx);
+  snprintf(priv->name, NAME_MAX, "/dev/console"); //// Previously: /dev/ttyV0
   ret = uart_register(priv->name, &priv->udev);
   if (ret < 0)
     {