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e200_opensource
e200_opensource PublicForked from SI-RISCV/e200_opensource
The Ultra-Low Power RISC Core
Verilog
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DDR2_Controller
DDR2_Controller PublicForked from adibis/DDR2_Controller
DDR2 memory controller written in Verilog
Verilog
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Design-and-Verification-of-DDR3-Memory-Controller
Design-and-Verification-of-DDR3-Memory-Controller PublicForked from tej-chavan/Design-and-Verification-of-DDR3-Memory-Controller
The memory model was leveraged from micron.
SystemVerilog
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DDR4MemoryController
DDR4MemoryController PublicForked from ananthbhat94/DDR4MemoryController
HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
SystemVerilog
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verilog
verilog PublicForked from seldridge/verilog
Repository for basic (and not so basic) Verilog blocks with high re-use potential
Verilog
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verilog-ethernet
verilog-ethernet PublicForked from alexforencich/verilog-ethernet
Verilog Ethernet components for FPGA implementation
Verilog
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