An interactive REPL for CPU architecture emulation.
D Python
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bootstrap.py
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README

            == DAREPL: D Architecture REPL ==

                -- Introduction --

DAREPL (short for D Architecture REPL) is a developer tool that lets you
interactively type in assembly instructions for a specific target CPU
and watch the effect they have on the machine state.

For further information, see:

    * LICENSE
      - Licensing and copyright information.
    * COMPATIBILITY
      - Supported compilers, architectures, operating systems, etc.
    * INSTALL
      - Instructions on building and installing DAREPL.
    * AUTHORS
      - Names and contact information for DAREPL developers.
    * STYLE
      - Coding style rules (only relevant if you're a contributor).

You can reach the DAREPL community in several ways:

    * IRC channel
      - #lycus @ irc.oftc.net
    * Mailing lists
      - lycus-announce: http://groups.google.com/group/lycus-announce
      - lycus-discuss: http://groups.google.com/group/lycus-discuss
      - lycus-develop: http://groups.google.com/group/lycus-develop