sayma: use GTP_CLK1 to clock DRTIO satellite transceiver

This is required to get constant skew between the DRTIO transceiver clock
(which then generates the RTIO clock) and the siphaser reference clock.

Both the Si5324 and the RTM clock tree have non-deterministic in-to-out skew
at 150MHz due to dividers.

artiq/firmware/satman/main.rs

@@ -270,13 +270,13 @@ pub extern fn main() -> i32 {
 
     i2c::init();
     si5324::setup(&SI5324_SETTINGS, si5324::Input::Ckin1).expect("cannot initialize Si5324");
+    #[cfg(has_hmc830_7043)]
+    /* must be the first SPI init because of HMC830 SPI mode selection */
+    hmc830_7043::init().expect("cannot initialize HMC830/7043");
     unsafe {
         csr::drtio_transceiver::stable_clkin_write(1);
     }
 
-    #[cfg(has_hmc830_7043)]
-    /* must be the first SPI init because of HMC830 SPI mode selection */
-    hmc830_7043::init().expect("cannot initialize HMC830/7043");
     #[cfg(has_ad9154)]
     let mut ad9154_initialized = false;
     #[cfg(has_allaki_atts)]

artiq/gateware/targets/sayma_amc.py

@@ -552,7 +552,7 @@ def __init__(self, with_sawg, **kwargs):
 
         self.comb += platform.request("sfp_tx_disable", 0).eq(0)
         self.submodules.drtio_transceiver = gth_ultrascale.GTH(
-            clock_pads=platform.request("si5324_clkout"),
+            clock_pads=platform.request("dac_refclk", 0),
             data_pads=[platform.request("sfp", 0)],
             sys_clk_freq=self.clk_freq,
             rtio_clk_freq=rtio_clk_freq)