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rtio/ttl_serdes_7series: reset IOSERDES (#958)
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sbourdeauducq committed Mar 14, 2018
1 parent 2fdc180 commit a315ecd
Showing 1 changed file with 4 additions and 2 deletions.
6 changes: 4 additions & 2 deletions artiq/gateware/rtio/phy/ttl_serdes_7series.py
Original file line number Diff line number Diff line change
Expand Up @@ -17,11 +17,12 @@ def __init__(self, pad, pad_n=None):
p_DATA_RATE_OQ="DDR", p_DATA_RATE_TQ="BUF",
p_DATA_WIDTH=8, p_TRISTATE_WIDTH=1,
o_OQ=pad_o, o_TQ=self.t_out,
i_RST=ResetSignal("rio_phy"),
i_CLK=ClockSignal("rtiox4"),
i_CLKDIV=ClockSignal("rio_phy"),
i_D1=o[0], i_D2=o[1], i_D3=o[2], i_D4=o[3],
i_D5=o[4], i_D6=o[5], i_D7=o[6], i_D8=o[7],
i_TCE=1, i_OCE=1, i_RST=0,
i_TCE=1, i_OCE=1,
i_T1=self.t_in)
if pad_n is None:
self.comb += pad.eq(pad_o)
Expand Down Expand Up @@ -54,7 +55,8 @@ def __init__(self, pad, pad_n=None):
i_D=pad_i,
i_CLK=ClockSignal("rtiox4"),
i_CLKB=~ClockSignal("rtiox4"),
i_CE1=1, i_RST=0,
i_CE1=1,
i_RST=ResetSignal("rio_phy"),
i_CLKDIV=ClockSignal("rio_phy"))
if pad_n is None:
self.comb += pad_i.eq(pad)
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