clean up hmc7043 reset

m-labs · Jun 5, 2018 · af88c4c · af88c4c
1 parent 988054f
commit af88c4c
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Showing 3 changed files with 6 additions and 8 deletions.
diff --git a/artiq/firmware/libboard_artiq/hmc830_7043.rs b/artiq/firmware/libboard_artiq/hmc830_7043.rs
@@ -229,7 +229,7 @@ pub mod hmc7043 {
         info!("enabling hmc7043");
 
         unsafe {
-        csr::crg::hmc7043_rst_write(0);
+            csr::hmc7043_reset::out_write(0);
         }
 
         spi_setup();

diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py
@@ -19,11 +19,8 @@
 from artiq import __version__ as artiq_version
 
 
-class CRG(Module, AutoCSR):
+class CRG(Module):
     def __init__(self, platform):
-
-        self.hmc7043_rst = CSRStorage(reset=1)
-
         self.clock_domains.cd_sys = ClockDomain()
         self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
         self.clock_domains.cd_clk200 = ClockDomain()
@@ -113,7 +110,6 @@ def __init__(self, platform):
         csr_devices = []
 
         self.submodules.crg = CRG(platform)
-        csr_devices.append("crg")
 
         clk_freq = 125e6
 
@@ -179,7 +175,9 @@ def __init__(self, platform):
             platform.request("ad9154_spi", 0),
             platform.request("ad9154_spi", 1)))
         csr_devices.append("converter_spi")
-        self.comb += platform.request("hmc7043_reset").eq(self.crg.hmc7043_rst.storage)
+        self.submodules.hmc7043_reset = gpio.GPIOOut(
+            platform.request("hmc7043_reset"), reset_out=1)
+        csr_devices.append("hmc7043_reset")
 
         # AMC/RTM serwb
         serwb_pads = platform.request("amc_rtm_serwb")

diff --git a/conda/artiq-dev/meta.yaml b/conda/artiq-dev/meta.yaml
@@ -15,7 +15,7 @@ requirements:
     - python >=3.5.3,<3.6
     - setuptools 33.1.1
     - migen 0.7 py35_35+git9bc084a
-    - misoc 0.11 py35_15+git7f63aff5
+    - misoc 0.11 py35_18+gitfb92c5ee
     - jesd204b 0.6
     - microscope
     - binutils-or1k-linux >=2.27